Issue 23, 2021
From the journal:

Nanoscale

Correction: 12-state multi-level cell storage implemented in a 128 Mb phase change memory chip

Zhitang Song,*a   Daolin Cai,*a   Yan Cheng,b   Lei Wang,c   Shilong Lv,a   Tianjiao Xina  and  Gaoming Fengc  

* Corresponding authors

a State Key Laboratory of Functional Materials for Informatics, Shanghai Institute of Micro-system and Information Technology, Chinese Academy of Sciences, Shanghai 200050, China
E-mail: ztsong@mail.sim.ac.cn, caidl@mail.sim.ac.cn

b Key Laboratory of Polar Materials and Devices (MOE), Department of Electronics, East China Normal University, Shanghai 200241, China

c Semiconductor Manufacturing International Corporation, Shanghai 201203, China

Abstract

Correction for ‘12-state multi-level cell storage implemented in a 128 Mb phase change memory chip’ by Zhitang Song et al., Nanoscale, 2021, DOI: 10.1039/d1nr00100k.

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Article information

DOI
https://doi.org/10.1039/D1NR90100A
Article type
Correction
Submitted
04 May 2021
Accepted
04 May 2021
First published
25 May 2021
This article is Open Access
Creative Commons BY license

Nanoscale, 2021,13, 10608-10609

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Correction: 12-state multi-level cell storage implemented in a 128 Mb phase change memory chip

Z. Song, D. Cai, Y. Cheng, L. Wang, S. Lv, T. Xin and G. Feng, Nanoscale, 2021, 13, 10608 DOI: 10.1039/D1NR90100A

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