A facile route to Si nanowire gate-all-around field effect transistors with a steep subthreshold slope

Abstract

We present a facile CMOS-compatible fabrication of lateral gate-all-around (GAA) field effect transistors (FETs) based on concentric Si–SiO₂/N⁺⁺Si core–multi-shell nanowires (NWs). Si–SiO₂/N⁺⁺Si core–multi-shell NWs were prepared by sequential Si NW growth, thermal oxidation and Si deposition processes in a single chamber. The GAA NW FET was then fabricated using the Si core, SiO₂ inner-shell, N⁺⁺ Si outer-shell as a channel, gate dielectric, and gate electrode, respectively. A one-step wet etching process was able to define the gate and source–drain contact regions. The SiNW GAA FET clearly exhibits a geometry-dependent gating effect and a steep subthreshold slope due to the low interface trapped charge density at the interface of the Si core and the SiO₂ shell. Our proposed SiNW GAA structures offer new opportunities for low-energy-consumption digital device applications.