High-performance carbon nanotube network transistors fabricated using a hole punching technique

Abstract

We develop a unique approach for fabricating high-performance carbon nanotube network transistors based on lithographic density control via a hole punching technique. In an as-grown dense network of single-walled carbon nanotubes (SWNTs), approximately two-thirds of the tubes are semiconducting and one-third are metallic, leading to a poor on/off ratio (<10). Altering the percolation threshold by reducing the density of SWNTs or by elongating the channel length may improve the on/off ratio, but the on current of a device prepared from such networks will decrease as a result. In this work, we intentionally relocate the percolation threshold of a SWNT network by drilling holes into the SWNT channels. Devices prepared using this approach displayed on/off ratios exceeding >10 000, with a high yield (>85%) and a large carrier mobility (20 cm² V⁻¹ s⁻¹). The on current degradation is not severe, unlike the degradation in networks prepared with a homogeneous density. The hole punching technique introduced here may be applied to network SWNT field effect transistor applications and provide new opportunities for controlling the properties of one-dimensional nanostructured percolating systems.