Optimal design for a high performance H-JLTFET using HfO2 as a gate dielectric for ultra low power applications

Abstract

In this paper we have proposed an optimal design for a hetero-junctionless tunnel field effect transistor (TFET) using HfO₂ as a gate dielectric. The device principle and performance are investigated using a 2D simulator. During this work, we investigated the transfer characteristics, output characteristics, transconductance, G_m, output conductance, G_D, and C–V characteristics of our proposed device. Numerical simulations resulted in outstanding performance of the H-JLTFET resulting in I_ON of ∼0.23 mA μm⁻¹, I_OFF of ∼2.2 × 10⁻¹⁷ A μm⁻¹, I_ON/I_OFF of ∼10¹³, sub-threshold slope (SS) of ∼12 mV dec⁻¹, DIBL of ∼93 mV V⁻¹ and V_th of ≃0.11 V at room temperature and V_DD of 0.7 V. This indicates that the H-JLTFET can play an important role in the further development of low power switching applications.