Correlation between gate-dielectric morphology at the nanoscale and charge transport properties in organic field-effect transistors

Abstract

The correlation between gate dielectric structure and processing, the resulting morphologies and field-effect charge carrier mobilities in generic organic semiconductors is investigated in prototype polymeric gate dielectric materials by an integrated computational approach based on atomistic molecular dynamics and kinetic Monte Carlo calculations. Our results indicate the critical role of dielectric heat treatments and provide a detailed picture of the phenomena involved. Namely, structural properties of the dielectric layer averaged over large surface areas, such as the root-mean-square roughness, do not completely account for the observed change in mobility in different samples. Inversely, calculations indicate local aggregation of polymer chains at the nanometer and sub-nanometer scale as one of the critical factors affecting charge carrier mobility. Indeed, the occurrence of asperities on the exposed dielectric surface hinders the formation of ordered and connected layers of organic semiconductors, thus constituting a detrimental factor for charge percolation. Accordingly, the thermal treatment of dielectric substrates has the potential of improving overall device performance by inducing polymer aggregation. Moreover, the propensity of the polymer dielectric material to form globular structures also affects the device properties, and hence a generalized model correlating the structural parameters of individual polymer chains with computed device mobilities is proposed.