The impact of atomic layer deposited SiO2 passivation for high-k Ta1−xZrxO on the InP substrate

Abstract

Metal–oxide-semiconductor (MOS) capacitors with an amorphous Ta_1−xZr_xO composite gate dielectric film and a SiO₂ passivation layer were fabricated on an indium phosphide (InP) substrate. To investigate the impact of the passivation layer, the interfacial chemical, physical and electrical properties of the Ta_1−xZr_xO/InP and Ta_1−xZr_xO/SiO₂/InP MOS structures were studied in detail. Electrical conductivity measurements combined with chemical bonding analysis using X-ray photoelectron spectroscopy (XPS) and electron dispersive spectroscopy (EDS) were conducted in order to evaluate the suitability of a Ta_1−xZr_xO alloy as a gate dielectric film for an InP substrate. XPS results showed that the Ta_1−xZr_xO film retained its insulating characteristics and was thermally stable even after annealing at 500 °C. However, Fermi-level pinning and significant diffusion of indium through the Ta_1−xZr_xO were observed. The diffusion of In was remarkably reduced after introducing the SiO₂ passivation layer, which resulted in an overall reduction in interfacial layer thickness. Parallel conductance contour measurements showed that the SiO₂ passivation layer resulted in unpinning of the Fermi-level. The introduction of a SiO₂ passivation layer with the Ta_1−xZr_xO composite gate dielectric film was found to provide remarkably improved dielectric performance, which was mainly attributed to reduced In diffusion and the passivation of interfacial and bulk dielectric defects.