Graphene–CNT hetero-structure for next generation interconnects

Abstract

Carbon nanomaterials, graphene and carbon nanotubes (CNTs), are emerging as potential materials proposed for integration in the future semiconductor technologies, and have been included in the ‘International Technological Roadmap for Semiconductors’ future plans (ITRS 2012). The main strength of these carbonaceous nanomaterials lies in their well-known advantageous electrical characteristics, namely low-resistivity, high current density ∼10⁹ A cm⁻², long electron mean-free-paths on the order of the sub-mm range and also their 10 times higher thermal conductivity as compared to copper. A rather uncommon combination of several beneficial electrical, thermal and physical characteristics has made them a strong contender for the replacement of metals in interconnects for the future Very Large Scale Integration (VLSI) and Ultra Large Scale Integration (ULSI) technologies. However, up to now unexpectedly high contact-resistances at the carbon/metal interfaces have presented a stiff technological challenge, hindering the large-scale adoption of the carbon-technology to replace the metals in interconnects in the semicon industry. The technological development for the implementation of graphene and CNTs inside the Through Silicon Via (TSV) structures for 3D-IC packaging, for Back-End-Of-Line (BEOL) and inter-chip interconnects is a real challenge. Although several reports have mentioned graphene or CNT based interconnects with metals, the main disadvantage lies at the carbonaceous materials-to-metal interface. A novel growth and fabrication technique is demonstrated for the heterostructure of the CNT/graphene materials to replacing horizontal metal lines, and metals in vertical interconnects. We have developed a process-flow for low-temperature (∼550 °C) growth of CNTs on top of semi-metallic few-layer graphene (FLG). In this approach, CNTs replace conventional metals in the vertical interconnects, while graphene is used to replace the traditional horizontal metal-lines on the integrated chips (IC) at the back-end level; and at the inter-chip interconnect level using TSVs, the innovative idea is to create a low-resistance CNT/graphene connection at their mutual interfaces for high-speed signal propagation, which is realized by the formation of covalent (sp²) bonds between carbon atoms in the CNT and FLG. The measurement under 2 μm diameter oxide via shows that R_FLG/CNT is about 1/6th of the R_Cu/CNT, and is about 1/15th of the total via resistance, which will initiate the large-scale adoption of the carbon-technology to replace metals in next generation interconnects.