Facile 3D integration of Si nanowires on Bosch-etched sidewalls for stacked channel transistors

Abstract

Three-dimensional (3D) integration is a promising strategy to integrate more functions into a given footprint. In this work, we report on a convenient new strategy to grow and integrate high density Si nanowire (SiNW) arrays on the parallel sidewall grooves formed by Bosch etching, via a low temperature (<350 °C) in-plane solid–liquid–solid (IPSLS) mechanism. It is observed that both the pitch and the depth of the grooves can be reliably controlled, by tuning the Bosch etching parameters, to adjust the density of SiNWs, and the sidewall growth of SiNWs is rather stable even along the turnings. This approach has demonstrated a facile batch-manufacturing of stacked SiNWs, where the SiNWs exhibit a mean diameter of 40 nm and a spacing of 100 nm, without the use of any high resolution lithography. Prototype stacked channel transistors are also fabricated, with an impressive on/off current of >10⁷ and a hole mobility of 57 cm² V⁻¹ s⁻¹, in a unique vertical side-gate configuration. These results highlight the unique potential and benefit of combining conventional Bosch processing with high precision 3D guided growth of SiNWs for constructing more complex and functional stacked channel electronics.