Vertically stacked SnSe homojunctions and negative capacitance for fast low-power tunneling transistors

Abstract

The two-dimensional (2D) vertical van der Waals (vdW) stacked homojunction is an advantageous configuration for fast low-power tunneling field effect transistors (TFETs). We simulate the device performance of the sub-10 nm vertical SnSe homojunction TFETs with ab initio quantum transport calculations. The vertically stacked device configuration has an effect of decreasing leakage current when compared with its planar counterpart due to the interrupted carrier transport path by the broken connection. A subthreshold swing over four decades (SS_{ave_4 dec}) of 44.2–45.8 mV dec⁻¹ and a drain current at SS = 60 mV dec⁻¹ (I₆₀) of 5–7 μA μm⁻¹ are obtained for the optimal vertical SnSe homojunction TFET with L_g = 10 nm at a supply voltage of 0.5–0.74 V. In terms of the device's main figures of merit (i.e., on-state current, intrinsic delay time, and power delay product), the vertical SnSe TFETs and NCTFETs outperform the 2022 and 2028 targets of the International Technology Roadmap for Semiconductors requirements for low-power application (2013 version), respectively.