Can ultra-thin Si FinFETs work well in the sub-10 nm gate-length region?

Abstract

Fin field-effect transistors (FinFETs) dominate the present Si FETs. However, when the gate length is scaled down to the sub-10 nm region, the experimental Si FinFETs suffer from poor performance due to a large fin width (the minimum value is 3 nm). In this paper, an ultra-thin Si FinFET with a width of 0.8 nm is investigated for the first time by utilizing ab initio quantum transport simulations. Remarkably, even with the gate length down to 5 nm, the on-state current, delay time, power dissipation, and energy-delay product of the optimized perfect ultra-thin Si FinFET still meet the high-performance applications’ requirements of the International Technology Roadmap for Semiconductors in the next decade. The overall performance of the simulated ultra-thin Si FinFET is even comparable with that of the typical two-dimensional FETs. Such a good performance can be significantly degraded by the defect. Hence, Si FinFETs have the potential to be scaled down to the sub-10 nm gate length as long as the width is scaled down while keeping a perfect structure.