Gate-bias instability of few-layer WSe2 field effect transistors

Abstract

Semiconducting two-dimensional (2D) layered materials have shown great potential in next-generation electronics due to their novel electronic properties. However, the performance of field effect transistors (FETs) based on 2D materials is always environment-dependent and unstable under gate bias stress. Here, we report the environment-dependent performance and gate-induced instability of few-layer p-type WSe₂-based FETs. We found that the hole mobility of the transistor drastically reduces in vacuum and further decreases after in situ annealing in vacuum compared with that in air, which can be recovered after exposure to air. The on-current of the WSe₂ FET increases with positive gate bias stress time but decreases with negative gate bias stress time. For the double sweeping transfer curve, the transistor shows prominent hysteresis, which depends on both the sweeping rate and the sweeping range. Large hysteresis can be observed when a slow sweeping rate or large sweeping range is applied. In addition, such gate-induced instability can be reduced in vacuum and further reduced after in situ vacuum annealing. However, the gate-induced instability cannot be fully eliminated, which suggests both gases adsorbed on the device and defects in the WSe₂ channel and/or the interface of WSe₂/SiO₂ are responsible for the gate-induced instability. Our results provide a deep understanding of the gate-induced instability in p-type WSe₂ based transistors, which may shed light on the design of high-performance 2D material-based electronics.