A high-performance logic inverter achieved using mixed-dimensional WSe2/n+-Si and MoS2/p+-Si junction field-effect transistors

Abstract

WSe₂, a transition-metal dichalcogenide, has been widely investigated as a next-generation semiconducting material owing to its unique physical properties. However, device degradation of the WSe₂ channel is inevitable in a metal-oxide-semiconductor structure because of the interface states. One of the solutions to this problem is to use insulator-less structures, such as metal-semiconductor field-effect transistors (FETs) or junction field-effect transistors (JFETs). We demonstrate a high performance logic inverter using JFETs with a mixed dimensional structure of transition-metal dichalcogenides and silicon materials. We apply WSe₂ and an n⁺-Si substrate as a p-type JFET device, whereas MoS₂ and a p⁺-Si substrate as an n-type JFET device. The fabrication process of the n-type device is similar to that reported in our previous study. The p-type properties of WSe₂/n⁺-Si JFETs are enhanced through surface polymer doping using the perfluoro-(butenyl vinyl ether) (PBVE) coating. The hole carrier concentration, on-current and contact resistance values of the WSe₂ JFETs are improved after the doping process. In contrast, as a trade-off, mobility and noise characteristics deteriorate after doping because of the surface scattering effect. Finally, we demonstrate a logic inverter by connecting a PBVE-coated WSe₂/n⁺-Si JFET and an n-type MoS₂/p⁺-Si JFET. Our results present an easy doping method applicable to JFET structures to achieve high performance.