Enhanced linear and symmetric synaptic weight update characteristics in a Pt/p-LiCoOx/p-NiO/Pt memristor through interface energy barrier modulation by Li ion redistribution

Abstract

Artificial synaptic devices have been extensively investigated for neuromorphic computing systems, which require synaptic behaviors mimicking the biological ones. In particular, a highly linear and symmetric weight update with a conductance (or resistance) change for potentiation and depression operation is one of the essential requirements for energy-efficient neuromorphic computing; however, it is not sufficiently met. In this study, a memristor with a Pt/p-LiCoO_x/p-NiO/Pt structure is investigated, where a low interface energy barrier between the Pt electrode and the NiO layer makes for a more linear and symmetric conductance change. In addition, the use of voltage-driven Li⁺ ion redistribution in the NiO layer facilitates the analog conductance change at a low voltage. Besides the linear and symmetric potentiation and depression weight updates, the memristor exhibits various synaptic characteristics such as the dependence of weight update on the pulse amplitude and number, paired pulse facilitation, and short-term and long-term plasticity. The conductance modulation is thought to be induced by a tunable interface energy barrier at the NiO layer and Pt bottom electrode, as a result of Li⁺ ion diffusion in NiO supplied from the LiCoO_x layer and their redistribution. Thanks to the use of Li⁺ ion redistribution, the conductance change could be achieved at a voltage <4 V within the time of μs range. These results verify the potential of artificial synapses with the Pt/LiCoO_x/NiO/Pt memristor operated by voltage-driven Li⁺ ion redistribution under the low interface energy barrier conditions, realizing a highly linear and symmetric weight update at a low voltage with a high speed for energy-efficient neuromorphic computing systems.