Ferroelectrically gated sub-6 nm monolayer MoS2 transistors for high-performance and low-power applications

Abstract

Driven by the development of big data and the Internet of Things, the emerging in-memory computing electronics based on non-volatile memory with merged logic-memory functionalities are becoming competitive. Herein, based on the significant polarization-tunable interface contacts in the sub-6 nm ferroelectric field-effect transistor (FeFET) composed of a monolayer MoS₂ channel and an h-BN insulated interlayer integrated with the thermodynamically stable ferroelectric BiAlO₃(0001) (BAO) polar surface, the quantum transport performance and application prospects of such a FeFET are further investigated using first-principles density-functional theory combined with non-equilibrium Green's function. The study finds that for the case of upward-polarization BAO, the on-state current is respectively ∼1022 and ∼620 μA μm⁻¹ for the high performance (HP) and low power (LP) applications of International Technology Roadmap for Semiconductors in 2013 version (ITRS 2013), both of which are much higher than the criteria of 900 and 295 μA μm⁻¹, respectively, suggesting that the FeFET is attractive for both HP and LP applications of ITRS 2013. However, for the case of downward polarization, the FeFET does not meet the requirements for both HP and LP applications of ITRS 2013. Nevertheless, a large tunneling electroresistance effect is expected to occur in the device, suggesting that it is promising for in-memory computing applications.