Nanotrapping memories

Abstract

Electrical memories have been vital to our everyday life, and their impact will be more significant in a future that is data-centric, sensor-equipped, and artificial-intelligence-powered. This review aims at discussing advances in nanotrapping memories, a term that is coined to embrace devices that functionally rely upon embedded nanoscale charge-trapping objects. The rationalization, demonstrations, and engineering concepts suggest that nanotrapping memories position themselves as a promising platform for both traditional and bio-inspired hardware architectures, and that their strong materials emphasis fuels the upcoming interdisciplinary nanoscience research.

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Chang-Hyun Kim

Chang-Hyun Kim is an Assistant Professor of Electronic Engineering at Gachon University. He received his PhD in physics from the École Polytechnique, France, in 2013, and conducted postdoctoral research at Columbia University, the French National Centre for Scientific Research (CNRS), and Gwangju Institute of Science and Technology, before joining the faculty in 2018. His current research focuses on the development of novel electronic devices based on organic semiconductors and hybrid nanoarchitectures. Prof. Kim was a recipient of the Alliance Doctoral Mobility Award, the Prix de thèse (PhD thesis award) of the École Polytechnique, the Korean Ministry of Education Research Fellowship, and the IEEE International Symposium on Next-Generation Electronics Best Paper Award.

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1 Introduction

The Internet-of-things (IoT) is a concept that is constantly evolving, and broadly describes a network of electronic systems such as phones, TVs, home appliances, and vehicles, where each component communicates with another via the Internet to provide a highly automatized and customized service.^1–4 Therefore, it represents a clear vision of an ultra-connected society and its world-wide market is expected to experience an unprecedented rapid growth.⁵ Not just because it sometimes aims at ‘digitizing’ the entire building or even cities,^6,7 the successful deployment of the IoT is conditioned by a multitude of sectors including consumer electronics, environmental engineering, computer science, informatics, as well as policies and marketing strategies.⁸ In particular, materials science can contribute enormously to this developmental context, because the necessity of electronic materials and devices suitable for new applications will sharply increase.

Memories are key ingredients of electronics, as they serve as a bridge between the sensing, processing, and communicating parts of any hardware architecture.⁹ In fact, the semiconductor memory industry is a mature one, making available a number of useful products. However, the requirements for next-generation memories should be different from those already in use, when thinking about the IoT and associated areas where the physical shape, tunability, and adaptability of devices become more critical than in traditional settings.^10,11 Recognizing this opportunity, there has been a substantial expansion of research towards novel materials and multifunctional devices.^12–14 Nanomaterial-based memories are an outstanding candidate for portable, wearable, infrastructure-embedded, or implantable products, because of their competitiveness for ultimate scaling-down and controllability. The state-of-the-art devices with e.g. graphene,^15–17 carbon nanotubes,^18–20 Si nanowires,^21–23 or organic molecules^24–26 are evidencing their great promise.

In this review, the phrase ‘nanotrapping memories (NTMs)’ is proposed to collectively describe a special class of nanomaterial-enabled memory technologies. Roughly speaking, NTMs refer to a range of devices incorporating nanomaterials as controllable charge traps (a more precise definition and classifications will follow). We have recently noticed remarkable progress in these particular devices as a distinct building block, which exhibits a high degree of design freedom, a favorable mechanical form factor, and excellent multifunctionality. Therefore, it is timely to deliver an overview of this emerging nanoelectronics platform, which is expected to fit well into both traditional and unconventional systems, including neuro-inspired computing.^27–31

The remaining parts of the article are organized as follows. In Section 2, we first put forward a fresh look at two well-established concepts for building a solid foundation for novel memory devices. Section 3 illustrates the definition and key mechanisms of NTMs, and introduces their sub-categories. Section 4 then highlights some of the representative devices that strengthen the understanding of the operating principles and clarify the applicable areas. Section 5 offers a subjective view on how to successfully design and optimize future NTMs. Finally, Section 6 provides some concluding remarks. While NTMs can be created with various semiconductors, we restrict our attention to the organic-semiconductor-based ones, which we believe represent an ideal material combination towards mechanically flexible, low-cost/large-area-processable, and functionally tailored systems.^32–36

2 Thinking differently

2.1 Traps that are helpful

Almost all traits of an organic device find their origin in the molecular nature of the active layer.³⁸ While a van der Waals type solid is clearly attractive for low-temperature deposition and mechanical softness, characteristically weak intermolecular coupling leads to a substantially lower carrier mobility (compared to that of a bulk inorganic crystal), as well as a strong energetic disorder.^39–41 As a result, a majority of the organic semiconducting mediums, which are generally prepared as a thin film, contain a large density of charge traps.^42,43 Due to the same molecular landscape, these materials are also highly sensitive to interface chemistry, and specific functional groups and/or spontaneous charge transfer between the two materials can introduce additional surface traps.^44–48 Taking organic field-effect transistors (OFETs) as an example, these traps are generally responsible for a large hysteresis and/or a non-negligible bias-stress effect,⁴⁹ both of which are detrimental to the reliable circuit applications of transistors.

Although organic-based devices have been quite notorious for trap-related problems, it is actually not the traps themselves to be blamed but their uncontrollability. For instance, Fig. 1 shows a dual-sweep transfer characteristic (gate voltage V_Gversus drain current I_D) excerpted from a paper published in 2005 by Gu et al.³⁷ These data were obtained from a pentacene OFET with a SiO₂ dielectric. It is worth emphasizing that the observed ‘memory’ effect (i.e. two different I_D levels at the same V_G depending on the driving sequence) was not intended here and this particular OFET structure did not explicitly include any traditional kind of memory elements (e.g. a ferroelectric insulator or charge-storage electrode).¹² Instead, the hysteresis was most likely due to the combined effects of intrinsic traps within polycrystalline pentacene and interface traps of the hydroxyl groups.^50,51 Therefore, the real issue is the difficulty in having full control over these mechanisms, but if we could selectively eliminate some of the unnecessary traps while endowing the remaining traps with desired physical properties, it would eventually make up a useful memory device.

Fig. 1 Saturation-regime transfer characteristics of a pentacene OFET showing a considerable hysteresis (measured at a fixed drain voltage of −50 V). I_d: drain current, V_gs: gate voltage. Reproduced with permission. Copyright 2005, American Institute of Physics.³⁷

In fact, smart and purposeful engineering of trapping sites has become a reality thanks to the advances in materials and interface engineering,⁵² and emerging NTMs fully utilize this possibility of introducing and adjusting charge traps of different natures for the realization of advanced memory structures.

2.2 ‘Distributed’ floating gates

Since Kahng and Sze proposed the first nonvolatile memory device in 1967,⁵⁴ the concept of ‘floating gate’ has been broadly exploited.⁵⁵ As a classical picture of EEPROM (electrically erasable and programmable read-only memory) in Fig. 2 suggests, a floating gate refers to the (usually metallic) electrode that is sandwiched between two dielectrics.⁵³ The name originates from the fact that a floating gate is usually embedded in a single dielectric medium (the electrode looks like it is ‘floating’ inside, which actually blurs the distinction between the two oxides). What is expected from this characteristic stack dictates the operating mechanism. Whether it is on a bulk MOSFET or a thin-film FET, the application of a V_G (at the control gate) leads to an electrical charging or discharging of the floating gate either by attracting charges from the channel or by releasing charges into the channel. This exchange of carriers is mediated by quantum mechanical tunneling or other injection mechanisms.⁵⁶ Eventually, these charges at the floating gate affect the applied gate field, thus altering the threshold voltage (V_T) of the transistor. In short, the data in a cell is stored as a charged state of the floating gate, which is read as a terminal voltage or a corresponding current.⁵⁷

Fig. 2 Cross-sectional illustration of a traditional floating gate EEPROM device. The thicknesses of the tunneling and blocking oxides are denoted as d₁ and d₂, respectively. Reproduced with permission. Copyright 1989, Institute of Electrical and Electronics Engineers.⁵³

The reason for revisiting the traditional floating gate effect here is that the basic mechanism is largely shared by NTMs. However, there are major differences that arise in terms of shapes and locations of floating materials, as well as their fabrication techniques, which are decisive factors that render NTMs highly tunable. First, nanomaterials in an NTM do not necessarily form a physically continuous layer while they can safely function as distributed and disconnected floating nodes. This underlines the possibilities for facile processing of a hybrid region where both dielectric and trapping materials are tightly intermixed. Second, the locations of floating gates can vary significantly from one device to another. A key to the function is the role of nanomaterials as externally controllable charge reservoirs, so they can even be placed in the semiconductor if efficient charge transfer can be maintained at the nanoscale. This aspect may weaken the appellation of floating ‘gates’ since the trapping materials do not always have to neighbor the gate or we can even build a device without any gate. In any case, when these materials are fully surrounded by a host matrix (either dielectric or semiconductor) and utilized as indirectly driven capacitors, the word choice is justified by both their appearance and mechanistic similarities. Third, in a classical floating gate device (such as that in Fig. 2), the three core layers (two dielectrics and the floating gate) are formally deposited, but in NTMs, manufacturing can be simplified in the cases where a nominally single material provides several properties. We will see below systems that employ surface self-oxidation or preliminary conformal capping for these purposes.

3 Definition and key mechanisms

The definition of an NTM is visually accentuated in Fig. 3. It broadly designates thin-film electronic memory devices, either diode- or transistor-type, where a variety of reduced-dimensional architectural ingredients function as structurally and operationally controllable charge-trapping physical sites. It differs from conventional memories in terms of material integrations, device structures, and extractable functionalities while it does not necessarily add a separate family to the traditional tree of memory technologies.⁵⁸ Rather, it is regarded as a new nanotechnological approach to offering improved or hybridized performances in several existing platforms.

Fig. 3 Concept of the NTM technology. The charge nanotrapping mechanism is assumed by various 1-D or 2-D materials with different natures and compositions. These nanoarchitectures are incorporated in the active layer or at the interfaces of a diode or transistor device to manifest memory functionalities.

From an electrical point of view, what is common in all different types of NTMs, many of which will be discussed in the next section, is that the incorporated nanomaterials play a crucial role in determining the macroscopic properties despite their small volume fraction. This important characteristic stems from their efficient charge-trapping and detrapping capabilities at normally non-trapping pathways. Fig. 4 illustrates two charge-trapping mechanisms relevant to NTMs. The energy-offset mechanism refers to the energetically driven movement of charge carriers to a stable trapping state and their subsequent immobilization. The trapped carriers have the chance to be detrapped back into the transport level getting thermal energy. This mechanism is dominant in a composite-type channel where a semiconductor and nanotraps form a uniformly mixed phase and the trap material provides a sufficiently deep quantum-well-like structure. The field-induced tunneling mechanism becomes critical when the nanotraps are surrounded by a dielectric (either as a surface capping or an external film). Depending on the direction and strength of the applied field, carriers tunnel into the nanotraps or escape back into the channel. While in Fig. 4 we employed the case of a biased diode and an accumulated transistor for the respective mechanism, it is for illustration purposes only, and the actual material characteristics and device geometry dictate which mechanism outperforms the other one, and both mechanisms can occur in both devices. When the trapping materials are uncharged or empty, the memory is said to be in its ‘erased state’ and it provides a certain level of intrinsic terminal current. After charging them in different fashions, the device is now in the ‘programmed state’ and the current becomes altered. This is a generic explanation that applies to both diode and transistor NTMs. For transistors, a V_T shift is often evoked to mention a state change. Although it seems natural to observe a lower current level in the programmed state (because we are talking about charges trapped), this is not always true because there are cases when the conduction carriers and trapped carriers are not of the same type, thus providing a larger density of counter charges and current when traps are occupied. Therefore, it is highly recommended to carefully establish a proper operating mechanism and analysis framework for each NTM, especially when we are presenting totally new materials or geometries.

Fig. 4 Energy diagrams illustrating characteristic charge-trapping and detrapping mechanisms. A hole-transporting semiconductor is assumed. Because of the dielectric nature of an organic medium, straight HOMO and LUMO levels appear in the diode architecture and the source injection barrier has direct implications in a transistor (E_F: Fermi level of the metal electrode).

Given the many different combinations of trapping materials, semiconductors, and device layouts, there are a virtually unlimited number of NTM variants. Nonetheless, in view of recent reports, we suggest categorizing them into two groups: NTMs with metallic nanostructures and those with carbon-based nanostructures. We will, from now on, exclusively deal with the devices that fall into either of these two sub-categories. Note that, among all possible structures (see Fig. 3), NTMs with non-carbon semiconducting trapping media will not be reviewed as they have not yet been investigated much. However, recently developed inorganic quantum dots (QDs) or hybrid perovskites are worth considering for a future generation of NTMs.^59–62

4 Recent developments

Here, a systematic overview of NTMs is provided with reported examples. Our focus is to clarify the materials choice, fabrication techniques, structural designs, interface phenomena, and physical mechanisms of representative systems. The uniqueness of each device will be also evaluated with its technological implications reassessed. In particular, we will separately discuss the applications of NTMs as conventional nonvolatile memory elements (used in traditional computing architecture) and as bio-inspired synaptic devices that are the foremost elements for the realization of neuromorphic computing. Note that, while we will be introducing many historically important devices, those that are showcased in Fig. 5–8 are the most recent achievements (published within the last five years) that best represent the current status of the field.

Fig. 5 Metal-nanostructure NTMs: conventional applications. (a) Device structure of an n-type diode memory with Al or Au NPs. The molecular structure of the semiconductor and the relevant energy levels are given. (b) Cyclic current–voltage characteristics showing a resistive switching behavior. (a and b) Reproduced with permission. Copyright 2015, Elsevier.⁶³ TEM images of (c) Au NPs and (d) Au@PPy core–shell NPs. (c and d) Reproduced with permission. Copyright 2018, Wiley-VCH.⁶⁴ (e) Structure of a pentacene OFET memory with bimetallic NPs. (f) Shift of the transfer curve upon gate programming and erasing (measured at a drain voltage of −3 V). (e and f) Reproduced with permission. Copyright 2015, Elsevier.⁶⁵

Fig. 6 Metal-nanostructure NTMs: neuromorphic applications. (a) A simple illustration of the biological signal transmission between neurons via a synaptic junction. (b) Structure and electrical configuration of the DNTT synaptic transistor (synapstor). (c) Spike-type input voltage signals. (d) Time-varying output currents measured from two different synapstors showing the STP behavior (inset: photograph of a flexible device array). (a–d) Reproduced with permission. Copyright 2016, Nature Publishing Group.⁶⁹ (e) The STP response amplitude versus the absolute value of the spike amplitude in pentacene–Au NP transistors. (f) Immuno-fluorescence image of SH-SY5Y grown and differentiated on EGOS. The red color is yielded by Alexa Fluor 594 immuno-label staining β-III tubulin. (e and f) Reproduced with permission. Copyright 2016, Elsevier.⁷⁰

Fig. 7 Carbon-nanostructure NTMs: conventional applications. (a) A structural illustration of the GQD-based memory transistor along with the chemical structures of the materials. (b) Repeated WRER cycling test using sequential V_G signals of 60, 0, −60, and 0 V at a V_D of −20 V. Inset: AFM topography of the pentacene layer. (a and b) Reproduced with permission. Copyright 2016, Institute of Physics.⁸⁰ (c) Structure of the resistive memory based on a PCBM + PVK active layer. (d) Cross-section of the device with 9 wt% PCBM. (e) Optical absorption spectra of the composite films with different PCBM contents. (f) Statistical analysis of the resistances at HRS and LRS. (c–f) Reproduced with permission. Copyright 2019, Elsevier.⁸¹

Fig. 8 Carbon-nanostructure NTMs: neuromorphic applications. (a) The structure of the flexible synaptic transistor with C₆₀ floating gates. (b) Gate-induced hole-trapping mechanism. (c) KPFM mapping of the trapping processes. (d) Temperature dependence of the relaxation time (E: activation energy). (e) Physiological learning, forgetting, and relearning experiences of the device. (a–e) Reproduced with permission. Copyright 2018, Wiley-VCH.⁹⁰

4.1 NTMs with metallic nanostructures

When a metal is embedded into a semiconductor, it provides a material-specific Fermi level that interacts with the transport levels of the surrounding host. Many organic semiconductors have a sizeable band gap, so a general energy diagram would facilitate carrier trapping by this metal rather than an injection from it (more discussion in Section 5.1). An early report by Ma et al. published in 2002 revealed a diode memory characteristic from an organic/metal/organic tri-layer sandwiched between an anode and a cathode.⁶⁶ A relatively thick Al layer (20 nm) was coupled with the organic semiconductor 2-amino-4,5-imidazoledicarbonitrile (AIDCN). Surprisingly, this unusual device exhibited a clearly identifiable ‘forming’ process and programmable current levels, which are seen in today's memristors.¹⁴ The exact mechanism was not fully accounted for at this time, but it is likely that both the intrinsic trapping at Al/AIDCN and the floating gate effect through the oxidized Al contributed to the memory behavior. This result stimulated further research and an important trend was to reduce the dimension of the metallic center by incorporating, for instance, metal nanoparticles (NPs). Many later studies investigated this organic–metal hybrid diode memory,⁶⁷ and among them, that by Bozano et al. published in 2005 demonstrated a series of tunable memory devices by varying both the semiconducting material and the spatial distributions of the NPs inside the active layer.⁶⁸

In 2015, Casula et al. reported on an air-stable, electron-transporting diode NTM (Fig. 5a and b).⁶³ The authors fabricated a vertical ITO (indium tin oxide)/N1400/NPs/N1400/Ag stack on glass with N1400 being the commercial name for a core-cyanated perylene derivative. The middle layer was composed of vacuum-evaporated Al or spray-coated Au NPs, to provide tunable morphologies and energy levels (Fig. 5a). Despite a substantial difference in their work functions, Al and Au NP based diodes showed similar resistive switching behaviors, as shown in Fig. 5b. We infer that this may reflect actual dissimilarities in the shapes and distributions of the NPs, and a thin surface alumina could also play a role. A high resistance ratio over 10³ was obtained between on- and off-states, and a long data retention time on the order of 10⁷ s was confirmed (for Au-NP devices). Importantly, the devices proved to be extremely stable in air, maintaining a reliable performance up to 16 months and enduring over 500 on–off cycling tests. Therefore, this device represents a promising platform that can satisfy a range of performance criteria (including long-term stability) critical to real applications.

A specific surface state (e.g. impurities or native oxides) may substantially contribute to the charge transfer kinetics at the metal/semiconductor interface, so probing and exploiting such nanoscale interfaces has become an important challenge. In this context, recent research on intentional pre-capping of NPs is worth discussing. In 2018, Zheng et al. demonstrated programmable negative differential resistance (NDR) in coplanar diodes made of self-assembled Au@polypyrrole (PPy) core–shell NPs (Fig. 5c and d).⁶⁴ They achieved a bottom-up synthesis of hybrid NPs from cationic radicals on a prepolymerized PPy chain adhering to electronegative Au. By this method, NP aggregation was avoided, and a uniform dispersion with a well-defined capping structure was obtained, as shown in the transmission-electron microscopy (TEM) image in Fig. 5c and d. A simple solution deposition completed the device, and they could selectively alter the core NP size (13 to 18 nm) and the polymer thickness (2 to 5 nm) to modulate the NDR characteristics.

The NPs-in-organic concept has also been widely employed in transistor devices.^71,72 Similar to diodes, the chemical nature, shape, and distribution of the NPs are shown to all be critical to the electrical properties, while a fundamental difference to take into consideration is the surface-conduction mechanism in FETs with a substantially larger carrier mobility (compared to bulk transport in diodes).⁷³ Also, the structural uniqueness of an OFET allows for the integration of NPs within the gate insulator, drawing additional possibilities for device engineering.^74–77 In 2015, Zhang et al. reported on advanced OFET NTMs incorporating bimetallic NPs (Fig. 5e and f).⁶⁵ These authors compared three cases: Ag-only, Pt-only, and Ag–Pt bimetallic NP arrays in the polystyrene (PS) dielectric. As shown in Fig. 5e, the Ag and Pt NPs were stabilized by oleic acid/oleylamine (OA) and polyvinylpyrrolidone (PVP), respectively. Pentacene was used as a p-type molecular semiconductor, in conjunction with Cu source/drain electrodes. A major finding was that the bimetallic NPs produce a synergistic effect. All three systems exhibited both positive and negative V_T shifts upon programming and erasing gate pulses. Interestingly, the memory windows (i.e. the entire V_T shift range upon programming–erasing) of the Ag- and Pt- samples were 8.8 and 9.9 V, respectively, while it increases up to 18.7 V when both particles are present (Fig. 5f). This enhancement was rationalized by more hole-selective trapping of Ag and electron-selective trapping of Pt, cooperating to hold the largest density of trapped charges in the bimetallic case. This result suggests that the hybridized use of nanotrapping materials can be a great strategy for the improvement of NTMs. Another possible location of a trapping layer in an OFET is at the interface between the gate dielectric and the semiconductor.⁷⁸ In 2016, our group published protein-capped Au NPs directly immobilized between SiO₂ and pentacene, which made up highly adjustable and large-area uniform memory transistors thanks to the dual properties of the protein molecules as a film-forming agent and an efficient tunneling dielectric.⁷⁹

Neuromorphic engineering is an emerging research area, which aims at building electronic systems that mimic the mechanisms of biological neurons and their interactions (Fig. 6a).^27–31 It is expected that the ultra-parallel and extremely energy-efficient function of neurons can revolutionize traditional computing architecture. Synaptic devices are key elements in an artificial neural network, and different memory structures with synapse-mimicking functionalities have been demonstrated. In 2016, our group reported on an NTM-type synaptic transistor (synapstor) on plastic (Fig. 6a–d).⁶⁹ Here, a few-nm-thick Al nanosheet was inserted between a poly(methyl methacrylate) (PMMA) dielectric and a dinaphtho[2,3-b:2′,3′-f]thieno[3,2-b]thiophene (DNTT) semiconductor.^82–84 The thermally evaporated conformal Al layer was readily surface-oxidized to become an Al SFG (self-formed floating gate), for the molecular channel to stay stable without electrical shorting (Fig. 6b). More importantly, the ultra-thin Al₂O₃ allowed for highly dynamic gate-driven trapping and natural detrapping of holes in the intact core Al region. Thanks to this structural arrangement, we successfully demonstrated the short-term plasticity (STP) of biological neurons in our devices, as shown by the constantly decreasing (depression) or increasing (potentiation) currents upon modulating the frequency of the input spike trains (Fig. 6c and d). This study therefore raised the potential of mechanically flexible electronics for wearable neuromorphic systems.

Building upon a series of their earlier work,^85–87 Desbief et al. reported in 2016 on an electrolyte-gated organic synapstor (EGOS) interfaced with real neurons (Fig. 6e and f).⁷⁰ In this study, an NTM structure is found in the pentacene–Au NP mixed active region. These authors specifically compared two driving schemes: the bottom-gate solid-state driving (‘synapstor in air’ in Fig. 6e) and the top electrolyte-gating using 0.1 M NaCl solution in water (‘EGOS’ in Fig. 6e). While the STP was systematically observed in both cases, the magnitude of the operating voltage varied significantly. The synapstors in air required a large voltage around 10 V, but the EGOS operated with a minimal voltage as low as 50 mV due to the strong capacitive coupling through electric double layers (EDLs) (Fig. 6e).⁸⁸ It is important to note that this voltage range is close to what the biological neurons transmit in their action potentials. Therefore, they made an attempt to build a direct neuronal interface using the EGOS. The suitability of a pentacene–Au film was tested by growing human neuroblastoma stem cells SH-SY5Y and NE-4C on top, and it was found to be a biocompatible substrate towards these cells (Fig. 6f). The device STP characteristics were not significantly affected by cell growth and differentiation, implying that neurons are weakly coupled to the transistor. We believe that the replacement of a biological synapse by an electronic one, or neuroprosthetics, might not be within the widespread interest of neuromorphics, but it might be something that organic systems will be able to ultimately accomplish.

4.2 NTMs with carbon nanostructures

The devices in which carbon-based nanomaterials undertake the nanotrapping function are discussed here. They are similar to the metal-based ones described above in that the shapes, properties, and locations of nanotraps are tailored to meet the specific performance requirements. Nonetheless, they can, in principle, provide a wider electronic tunability, because we can choose from 2-D materials such as graphene, semiconducting components (e.g. fullerenes) with a useful band gap, as well as mixed-dimensional, hybridized nanostructures.⁸⁹

In 2015, Park et al. reported on the controlled growth of a graphene charge-floating gate for memory transistors.⁹¹ They systematically varied the chemical vapor deposition (CVD) time of graphene on Cu foil from 1 to 60 s, to obtain partially connected ‘discrete’ nanosheets. An optimum material was obtained under the 40 s conditions to guarantee both a good coverage and in-plane discontinuity, which was claimed to be important for long-term charge storage. This graphene was transferred to be inserted between two dielectrics (SiO₂ and PS), on which a pentacene channel and Au source/drain electrodes were evaporated to complete the device. The insertion of graphene resulted in a hysteresis in the transfer curves, which was absent in the control device. Therefore, an NTM-type operation was successfully demonstrated, with graphene serving as distributed charge traps. The transistor exhibited a large memory window (∼40 V) and a long data retention time over 10⁵ s. In 2016, Ji et al. proposed an OFET memory with a solution-processed graphene quantum dot (GQD) layer (Fig. 7a and b).⁸⁰ Physical and chemical nanoengineering of graphene is an efficient technique to tune its electrical properties,⁹² and these authors utilized a modified thermal plasma jet method to produce high-crystallinity GQDs with suppressed oxidation. The materials were spin-cast onto SiO₂ and covered with a thin tunneling PS dielectric (Fig. 7a). The PS also planarized the QD surfaces, important for the growth of a pentacene film (inset of Fig. 7b). The final devices operated robustly with the on–off current ratio in excess of 10⁵, the retention time over 10⁴ s, and the confirmed endurance to 100 write/erase cycles. Fig. 7b is the result of a repeated write–read–erase–read (WRER) cycling test, showing the systematic transition between the on and off states. The electrical behaviors were explained by quantum confinement and level splitting in the GQDs, offering a carrier-trapping capability up to 7.2 × 10¹² charges per cm². These and related research evidence that graphene, prepared by various synthetic routes and with different shapes, can be a high-performance trap medium for both diode and transistor NTMs,^93,94 expanding its applicability beyond transparent electrodes.

Fullerene (C₆₀) and its derivatives have also received growing attention as a molecular memory ingredient.^95–98 A recent diode application can be found in the article by Sun et al. published in 2019 (Fig. 7c–f).⁸¹ Here, a vertical ITO/PCBM + PVK/Al stack was constructed on glass, where PCBM + PVK means a composite layer between [6,6]-phenyl-C₆₁-butyric acid methyl ester (PCBM) and poly(N-vinylcarbazole) (PVK) (Fig. 7c). Both of the organic semiconductors were dissolved in dichlorobenzene and blended in the solution phase, with three different mixing ratios (9, 23, and 41 wt% PCBM). They were co-deposited by spin-coating to form a homogeneous active layer of less than 100 nm, as shown by the scanning electron microscopy (SEM) image in Fig. 7d. The authors specifically addressed the effect of the blending ratio on the electrical properties. In optical absorption measurements on the active films (Fig. 7e), the weak absorption band around 923 nm decreased at high PCBM contents, manifesting an overall favorable charge transfer between the donor PVK and the acceptor PCBM at low concentrations. All the diode devices behaved as a resistive switching memory, with a strong ratio effect. As shown in Fig. 7f, the resistance ratio between the high-resistance state (HRS) and the low-resistance state (LRS) was the highest for the 9 wt% sample, with a value exceeding 10⁴, confirming that electronic coupling is the most pronounced under this condition. The devices were also shown to be highly non-volatile with an estimated retention time over 10⁵ s. This study therefore reveals that a purely organic blend with a substantial internal energetic mismatch can produce an all-organic NTM, by affording efficient charge trapping and retention even without any dielectric capping or blocking interlayer.

Neuromorphic applications of carbon-based NTMs have been suggested very recently. In 2018, Ren et al. reported on gate-tunable synaptic plasticity in fullerene composites (Fig. 8).⁹⁰ They synthesized a hybrid C₆₀/PMMA nanotrapping film by solution processing. As shown in Fig. 8a, such a film was inserted between an Al₂O₃ blocking insulator and a pentacene channel, and Ag gate and Au source/drain electrodes were used for the transistor. All materials were low-temperature-processed to build a plastic device, and the combination of thin dielectrics (30 nm Al₂O₃ and 75 nm PMMA) allowed for low-voltage operation at around 5 V. Following the conventional floating gate mechanism (reviewed in Section 2), the uniformly distributed fullerenes served as gate-controllable charge-trap centers. Under a negative V_G, holes from pentacene could tunnel into C₆₀ (Fig. 8b), and under a positive V_G, electron trapping occurred. Fig. 8c shows the Kelvin probe force microscopy (KPFM) image visualizing both a hole-trapping region (center) and an electron-trapping region (surroundings) in the C₆₀/PMMA film, with a measured potential difference of ∼500 mV between the two regions. After charging the fullerene nanotraps with either type of carriers, the natural detrapping (or relaxation) process was monitored. Fig. 8d is an Arrhenius analysis showing that electron detrapping is thermally activated, equivalent to the relaxation time (τ) decreasing with a temperature (T) increase. The manipulation of the carrier trapping at the time domain was combined with the natural relaxation to mimic a number of biological synaptic functions, e.g. excitatory postsynaptic current (EPSC), paired-pulse facilitation/paired-pulse depression (PPF/PPD), and transition from short-term to long-term potentiation. An interesting demonstration is shown in Fig. 8e, for the three repeated cycles of learning and forgetting. Here, a learning period corresponds to current enhancement by multiple positive V_G pulses, and forgetting is a detrapping relaxation. It was found that, between the two fixed current levels, a smaller number of ‘learning’ pulses were required with a slower relaxation when the process is repeated, reminding us of relearning with a human brain to keep old knowledge alive.

5 Design considerations

The comprehensive picture established in the previous section now allows us to see NTMs as a rapidly growing subject. Therefore, it seems difficult to grasp its full potential at this stage, and tremendous new opportunities are foreseeable. In this section, several key insights into how to create new devices with tailored functionalities are provided, as a guideline for future research endeavors.

5.1 Energetic alignments

As detailed in our previous reviews,^33,47 organic semiconductors are intrinsically reliant on an external charge supply due to their dielectric nature. Therefore, the energetic position of the frontier orbitals is the first to consider especially when designing an NTM with trapping inside the active layer (such as those in Fig. 5a and 7c, or NPs-in-channel OFETs^71,72). When we incorporate a metallic nanotrap, its proper functioning as traps is guaranteed when its Fermi level is positioned within the band gap of the contacting semiconductor.⁵⁶ In this sense, energetically deeper traps can provide a more pronounced effect with stronger device non-volatility (slower detrapping). In other words, the choice of a good ‘trapping’ metal for a given semiconductor generally goes in the opposite direction from how to select an efficient ‘injecting’ electrode. One can therefore refer to the available database (which actually mostly served the latter purpose) on the HOMO and LUMO levels of semiconductors and Fermi levels of metals in advance to pick ideal combinations.^47,99,100 For NTMs with a carbon-containing semiconducting trap, at least one of its frontier orbitals should be placed within the band gap of the host matrix to ensure efficient trapping.

When a dielectric is present between the nanotrap and the active material, either intentionally (e.g. self-assembled monolayers, core/shell architecture) or uncontrollably (e.g. native oxidation, mostly when Al is used), the pure energetic balance between the two media may eventually become less critical, because the tunneling and floating gate effects will enable the core to accommodate and hold trapped carriers.⁷⁹

Relevant energy levels can be substantially affected by processing or by an electric field, implying another important aspect to take into account. For example, Mosciatti et al. reported in 2015 on a multifunctional polymer–graphene transistor exploiting one of these secondary effects.¹⁰¹ In this study, liquid-phase exfoliated graphene (LPE-G) was directly solution-deposited on a dielectric to form disconnected islands, onto which a polymer semiconductor made up a transistor channel. It was found that the ionization energy of LPE-G is highly sensitive to post-deposition thermal annealing, with a value changing from 4.8 to 5.7 eV. Therefore, it was possible to use LPE-G either as a nanotrapping material or a conductive bridge inside the semiconductor, depending on its energy. Graphene's work function is also known to be strongly field-dependent, and this property gave birth to novel vertical heterojunction triodes.⁷³ Therefore, it is theoretically reasonable to expect a dynamic change of trapping levels in graphene or related materials inside an NTM under operating conditions.

5.2 Hierarchical features

Due to the soft molecular nature, the growth of an organic film is strongly affected by the underlying substrate.¹⁰² Furthermore, the nanoscale growth interface is believed to have a sequential bottom-up effect on the meso- to macroscopic properties through hierarchical mechanisms that are pronounced in organic-based systems. For instance, the molecular orientation of the same material, which can be tuned by the substrate chemistry, can have a broad impact on the injection barrier, carrier mobility, dielectric constant, emissive properties, and so on.^44,45,103

So, when incorporating a nanotrapping material, a careful consideration of its possible effects at various length scales is recommended, as it will enlighten an optimum material choice and an ideal device structure. Previous reports show that, when NPs are placed on a dielectric in a bottom-gate transistor, their roughness can prevent the growth of a high-mobility channel, and a trade-off between the memory and transport parameters may appear.^79,85 Therefore, sophisticated interface engineering is key. For instance, introducing specific chemical anchoring groups to a metal or dielectric surface has been an efficient approach to guiding crystallization and improving ‘planar’ organic devices.⁴⁶ We believe that a similar technique can be used in the context of NTMs, for the surface-functionalized nanotraps to provide an additional role as growth initiators and morphological modifiers, even though a more complex 3-D spread of the hierarchical forces will need to be elaborated.

5.3 Application horizons

To meet the increasingly strict requirements of mobile and wearable products, we can envision a newer generation of NTMs with additional potentially useful functionalities.

Firstly, known optical properties of nanomaterials can be utilized to make an optically controllable NTM. Optical memories are gaining increasing attention, because they have promise for fast and low-power programming and readout. For instance, a flexible optical memory transistor with over 256 distinct levels was demonstrated in 2016 by Leydecker et al. using a photochromic organic blend.¹⁰⁴ Nanoplasmonic effects of metal NPs and enhanced light–matter interactions are well-documented in solar cell research.¹⁰⁵ Therefore, plasmonic improvement of optical sensitivity in an organic–NP hybrid channel can be useful to construct high-performance photonic NTM structures.

Secondly, traditionally separated sensing and memory parts can be ideally merged into a single device. In particular, the development of bio-NTMs can be an interesting idea. In 2017, our group proved the biocompatibility of protein-self-assembled Au NPs,¹⁰⁶ the same material that was initially employed as a nanotrapping electrical component.⁷⁹ Many other reports support the possibility of combining memory and biological phenomena, such as those on deoxyribonucleic acid (DNA)–Ag nanocomplex memristors,¹⁰⁷ hysteresis-based Si nanowire biosensors,¹⁰⁸ and biodegradable skin-inspired resistive switching memories.¹⁰⁹

Thirdly, the energy consumption has not been addressed much, so the minimization of program/read voltages and static dissipation should be given a higher priority for technological advancements. Our expectation is that the characteristic operation relying on small-sized elements in NTMs would allow for the extreme scaling-down of the active layer and/or dielectric for a very-low-voltage device, and the inherently energy-efficient neuromorphic scheme could well serve this purpose. The ultimate goal in this direction might be a fully self-powered operation, enabled by flexible and ultra-light-weight energy harvesters (e.g. photovoltaics, thermoelectrics, etc.) integrated on-site along with sensing and memory components.¹¹⁰

We note that future research should aim at the areas that ideally leverage the unique properties of NTMs beyond traditional memory platforms. In this regard, a stronger emphasis on neuromorphic devices is deemed natural, given both the high promise of the technology and potentially many unrealized ways to combine nanotrapping and neuronal regimes. For the next-generation NTM synapses, structural miniaturization for biological signal compatibility, interface hybridization for operational stability, and cellular sensing and stimulating capabilities for prosthetic use can be some of the key drivers.

6 Conclusion

This review is intended to conceptualize NTMs and increase their visibility in nanoscience and electronics research. Although various devices discussed here might be originally developed under different names and motivations, a close look at their operating principles makes it logical and useful to group them into one technological stream and project their future in a unified framework. The importance of data and intelligent systems will continue to increase in our society, and it is believed that NTMs, with their versatility and flexible performances, can become a particularly promising candidate for next-generation memory technologies and unconventional on-demand platforms. Furthermore, it is anticipated that NTMs will grow to represent a cutting-edge interdisciplinary field with a clear target application, which therefore has the capacity to steer strong research efforts towards the discovery of ideal nanoscale materials and their advanced properties.

Conflicts of interest

There are no conflicts to declare.

Acknowledgements

This work was supported by the National Research Foundation of Korea (NRF) grant funded by the Korean government (Ministry of Science and ICT) (NRF-2019R1C1C1003356).

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