Rectifying optoelectronic memory based on WSe₂/graphene heterostructures

Abstract

van der Waals heterostructures composed of two-dimensional materials vertically stacked have been extensively studied to develop various multifunctional devices. Here, we report WSe₂/graphene heterostructure devices with a top floating gate that can serve as multifunctional devices. They exhibit gate-controlled rectification inversion, rectified nonvolatile memory effects, and multilevel optoelectronic memory effects. Depending on the polarity of the gate voltage pulses (V_Gp), electrons or holes can be trapped in the floating gate, resulting in rectified nonvolatile memory properties. Furthermore, upon repeated illumination with laser pulses, positive or negative staircase photoconductivity is observed depending on the history of V_Gp, which is ascribed to the tunneling of electrons or holes between the WSe₂ channel and the floating gate. These multifunctional devices can be used to emulate excitatory and inhibitory synapses that have different neurotransmitters. Various synaptic functions, such as potentiation/depression curves and spike-timing-dependent plasticity, have been also implemented using these devices. In particular, 128 optoelectronic memory states with nonlinearity less than 1 can be achieved by controlling applied laser pulses and V_Gp, suggesting that the WSe₂/graphene heterostructure devices with a top floating gate can be applied to optoelectronic synapse devices.

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Introduction

van der Waals (vdW) materials, such as graphene, semiconducting transition metal dichalcogenides, and hexagonal boron nitride (hBN), have received considerable attention owing to their possible applications in ultrathin, flexible, and transparent electronic and optoelectronic devices.^1–4 In particular, vdW heterostructures, in which different vdW materials are vertically stacked, have been extensively studied to develop multifunctional devices.^5–7 For example, various hybrid heterostructures, such as PtS₂/h-BN/graphene,⁸ graphene/hBN/MoS₂,y ⁹ MoS₂/hBN/graphene or MoS₂,¹⁰ and graphene/hBN/ReSe₂ ¹¹ exhibit multibit optoelectronic nonvolatile memory effects. When these heterostructures are irradiated with laser pulses, the conductance increases in a staircase behavior, enabling multilevel optical erasing, whereas multilevel programming is achieved by applying gate voltage pulses (V_Gp). In contrast to traditional random-access memories (RAMs), optoelectronic random-access memories (ORAMs) can store light information with an electronic readout at low programming voltages. Processing with light as an extra control parameter provides features such as optical and arithmetic logic operations and the simultaneous detection of electrical and optical signals. Furthermore, image-capturing circuits are simplified by the integration of optical sensors and memory devices in ORAMs.

Herein, we report a WSe₂/graphene heterostructure device with a photoresponsive top floating gate. The heterostructure without the top layer exhibited gate-tunable rectifying characteristics without memory effects, which is ascribed to the mismatch between the Fermi levels of graphene and WSe₂ and the ambipolar properties of WSe₂.¹² However, the heterostructure with a MoS₂ top layer exhibited rectifying nonvolatile memory effects with an on/off ratio of ∼10⁴ and a retention time of >10³ s, indicating that the MoS₂ top layer acts as a charge trapping layer or floating gate. Kelvin probe force microscopy (KPFM) images revealed that holes and electrons were trapped in the top floating gate by applying V_Gp < 0 and V_Gp > 0, respectively, resulting in rectifying nonvolatile memory behaviors. Furthermore, our devices exhibited multilevel optoelectronic memory effects. However, unlike most of the reported optoelectronic devices,^9–11 multilevel programming was achieved by repeated illumination, whereas multilevel erasing was obtained by repeated illumination with laser pulses combined with V_Gp.

These gate-tunable rectified multilevel optoelectronic memory properties will pave the way for various future applications. One potential application is in optoelectronic synapse devices. Recently, a variety of two-terminal memristors^13–16 and three-terminal devices^17–21 have been explored as artificial synapses for emulating biological synaptic functions. More recently, optoelectronic synapses based on MoO_x,²² phase-change materials,²³ and black phosphorous/P_xO_y ²⁴ have also been demonstrated. However, although there are two types of biological synapses, called excitatory and inhibitory synapses, which have different neurotransmitters,^25–27 most devices emulate only excitatory synapses. If excitatory neurotransmitters bind to receptors in a postsynaptic neuron, ligand-gated ion channels open and positive ions flow into the cell, generating excitatory postsynaptic currents (EPSCs). In contrast, if inhibitory neurotransmitters bind to receptors, negative ions flow into the cell through ion channels, generating inhibitory postsynaptic currents (IPSCs). For an action potential to occur, the sum of the EPSCs and IPSCs must exceed a threshold value. The balance between excitation and inhibition is very important in the brain. If the balance is disrupted, diseases such as epilepsy can occur.²⁸

To investigate whether rectified nonvolatile memory effects can be applied to emulate inhibitory synapses as well as excitatory synapses, two similar devices were connected in parallel. Similar to the addition of EPSCs and IPSCs, the total conductance increased or decreased depending on the polarity of V_Gp applied to the two devices. In addition, various synaptic functions, including potentiation and depression processes, and spike-timing-dependent plasticity (STDP) could be emulated, and the recognition rate was simulated to be approximately 72% using an artificial neural network (ANN) based on a single-layer perceptron (SLP) model. These results demonstrate that the WSe₂/graphene heterostructures with a top floating gate can be applied to optoelectronic synapse devices.

Results and discussion

Electrical characteristics of a WSe₂/graphene heterostructure

First, we fabricated a WSe₂/graphene heterostructure on an hBN (∼11 nm)/SiO₂/p⁺⁺-Si substrate with prepatterned Au electrodes to avoid the high Schottky barrier,^29,30 where a gate voltage (V_G) was applied using the p⁺⁺-Si substrate. Mechanically exfoliated few-layer graphene (∼12 nm) and WeS₂ flakes (∼10 nm) were transferred onto the electrodes, resulting in a WSe₂/graphene heterostructure (Fig. 1(a)). Initially, the source-drain current (I_SD)–voltage (V_SD) curve of this device showed negligible conductance (Fig. S1†). However, when the I_SD–V_G transfer curves were measured by sweeping V_G from −60 to +60 V and back to −60 V, p-type and n-type semiconducting behaviors were observed at V_SD = −1 and +1 V, respectively (Fig. 1(b)). Accordingly, when V_G ≪ 0, I_SD exhibited finite values at V_SD < 0, whereas I_SD was negligible at V_SD > 0, leading to rectifying characteristics (Fig. 1(c)). In contrast, when V_G ≫ 0, the rectification direction was inverted: I_SD was finite only for V_SD > 0. Similar gate-controlled rectifying behaviors have also been reported in other studies.^12,31,32

Fig. 1 (a) Schematic of a WSe₂ field-effect device with graphene and Au electrodes. (b) I_SD–V_G transfer curves measured at V_SD = −1 V (blue symbols) and +1 V (red symbols) by sweeping V_G from −60 to +60 and back to −60 V. The inset shows an optical image of the device. (c) I_SD–V_SD curves measured when different values of V_G were applied. (d) Energy band diagrams before applying V_G (top), with V_G ≪ 0 (middle) and V_G ≫ 0 (bottom).

This gate-tunable rectification inversion is explained by the energy band diagrams shown in Fig. 1(d). The bandgap (E_g) and electron affinity (χ) of the multilayer WSe₂ are approximately 1.3 and 3.5 eV, respectively,^33,34 and the workfunction (φ) is 4.56 and 5.1 eV for graphene and Au, respectively.^34,35 If V_G ≪ 0, the Fermi level shifts downward and the major charge carriers become holes. At V_SD < 0, the holes can move from the graphene to WSe₂, leading to finite currents. However, at V_SD > 0, the holes cannot flow into the graphene because of the gate-induced Fermi level mismatch between graphene and WSe₂, resulting in a rectifying behavior. In contrast, if V_G ≫ 0, the Fermi level shifts upward and the major charge carriers are electrons that can flow from the WSe₂ to the Au electrode only at V_SD > 0. Thus, the rectification direction is inverted.

Memory properties of a WSe₂/graphene heterostructure with a MoS₂ floating gate

Next, we fabricated a WSe₂/graphene heterostructure with a MoS₂ top layer by transferring hBN (∼10 nm) and MoS₂ (∼11 nm) flakes onto the heterostructure (Fig. 2(a)). The I_SD–V_G transfer curves, which were measured by sweeping V_G from −50 to +50 V and back to −50 V, showed n-type and p-type semiconducting behaviors at V_SD > 0 and V_SD < 0, respectively, as in the WSe₂/graphene heterostructure without the MoS₂ top layer (Fig. 2(b)). However, the I_SD–V_G transfer curves of this device exhibited large hysteresis for both polarities of V_SD, indicating that the MoS₂ top layer acted as the floating gate, although the MoS₂ layer was placed on the top of the heterostructure, unlike the conventional flash memory devices that have a floating gate between a channel and a control gate. To characterize the nonvolatile memory effects, V_Gp of −50 V or +50 V with a pulse width of 0.1 s was applied, and I_SD was measured at V_SD = +1 V (Fig. S2(a)†). The device was switched to the on state by applying V_Gp = −50 V and to the off state by applying V_Gp = +50 V. On the other hand, the application of V_Gp = −50 and +50 V induced the off and on states, respectively, at V_SD = −1 V. For both cases, the on/off ratio was ∼10⁴ and the retention time was estimated to be longer than 10³ s. To further investigate the nonvolatile memory properties, I_SD was measured when ±1 V square waves were applied to the V_SD after applying V_Gp with different amplitudes (Fig. 2(c)). The rectified multilevel memory states were obtained. When triangular waves were applied to V_SD after applying different V_Gp, similar rectified multilevel memory effects were also observed (Fig. S2(b)†).

Fig. 2 (a) Schematic of a WSe₂-based device with a MoS₂ top layer. (b) I_SD–V_G transfer curves measured at various V_SD by sweeping V_G from −50 to +50 V and back to −50 V. (c) I_SD measured at V_SD of ±1 V square waves with a frequency of 5 Hz after applying various V_Gp. Before each measurement, the device was reset by applying V_Gp = +60 (top) or V_Gp = −60 V (bottom). Energy band diagrams in (d) a flat band, (e) with V_Gp ≪ 0 and (f) V_Gp ≫ 0. χ represents an electron affinity. KPFM images acquired (g) before applying V_G, (h) after applying V_Gp = −50 V and (i) V_Gp = +50 V. Green, white, and red dashed lines indicate WSe₂, graphene, and MoS₂, respectively. (j) Line profile of KPFM signals indicated by arrow lines in (g), (h), and (i).

To explain the rectified nonvolatile memory effects, we propose the energy band diagrams shown in Fig. 2(d)–(f). If a negative voltage pulse with a large amplitude is applied to V_G, the Fermi level shifts downward, and the tunneling barrier is lowered (Fig. 2(e)). Consequently, holes can tunnel from the WSe₂ channel to the MoS₂ layer through the hBN. However, when V_G returns to 0 V, the tunneling barrier increases again, and the holes become trapped in the MoS₂ layer. The trapped holes shift the Fermi level upward, and the device is switched to the on state at V_SD > 0 and to the off state at V_SD < 0, as shown in Fig. 1(d). In contrast, if a positive voltage pulse with a large amplitude is applied to V_G, electrons tunnel from the WSe₂ channel to the MoS₂ layer via the Fowler–Nordheim tunneling mechanism, and are trapped in the MoS₂ floating gate (Fig. 2(f)), which results in the on state at V_SD < 0 and the off state at V_SD > 0. Fig. 2(g)–(i) show KPFM images acquired before applying V_Gp and after applying V_Gp = −50 and +50 V, respectively. Positive/negative KPFM signals indicate the accumulation of positive/negative charges,^36,37 and these KPFM images support that the rectified nonvolatile memory effects are attributed to the trapping of holes and electrons in the MoS₂ top floating gate induced by the application of V_Gp = −50 and +50 V, respectively (Fig. 2(j)).

Optoelectronic performances of a WSe₂/graphene heterostructure with a MoS₂ floating gate

Illumination with laser pulses was reported to induce multilevel memory states in MoS₂-based devices with a floating gate;^9,10 hence, we also investigated whether our WSe₂/graphene device with the MoS₂ top layer exhibited multilevel optical memory effects. First, the device was switched to the off state at I_SD = +1 V by applying V_Gp = +50 V, which induced electrons trapped in the MoS₂ layer and led to p-type behaviors. The light pulses were then illuminated (Fig. 3(a)). I_SD increased during irradiation but returned to the off state in dark, unlike most reported electronic memory devices, in which I_SD increased stepwise upon repeated illumination with laser pulses. In the case of our devices, holes should be trapped in the MoS₂ floating gate to obtain a stepwise increase in I_SD at V_SD = +1 V. These results imply that hole trapping was not induced by illumination. To make holes tunnel from WSe₂ to MoS₂, V_Gp ≪ 0 is required (Fig. 2(e)). When V_Gp = −25 or −32 V was repeatedly applied, I_SD increased in a staircase behavior (Fig. 3(b)). However, when V_Gp = −15 V was applied, the I_SD did not increase at all, implying that the tunneling barrier was not sufficiently lowered by V_Gp = −15 V.

Fig. 3 (a) I_SD measured at V_SD = +1 V when 532 nm laser pulses, V_Gp = −15 V, or 532 nm-laser pulses with V_Gp = −15 V were applied after applying V_Gp = +50 V. The dotted lines indicate when the laser pulses were applied. (b) I_SD measured at V_SD = +1 V when V_Gp = +50 V was applied to switch the device to the off state and then, V_Gp = −15, −25, or −32 V was repeatedly applied. The arrows indicate the time at which V_Gp was applied. (c) Energy band diagram proposed to explain the positive stepwise photoconductance. (d) I_SD measured at V_SD = +1 V when V_Gp = +50 V was applied to switch to the off state and then, 532 nm laser pulses (13 nW) and V_Gp = −5, −10, or −15 V were simultaneously applied. The dotted lines indicate when the laser pulses were applied, while the arrows indicate the time at which V_Gp was applied. (e) I_SD measured at V_SD = +1 V when V_Gp = −50 V was applied to switch the device to the on state and then, 532 nm laser pulses with a pulse width of 0.1 s and different powers were applied every 30 s. The dotted lines indicate the time when the laser pulses were applied. (f) Energy band diagram proposed to explain the negative stepwise photoconductance by light.

To facilitate the trapping of holes in the MoS₂ layer, the device was illuminated with 532 nm laser pulses while V_G = −15 V was applied (Fig. 3(a)). Although the tunnel barrier is not sufficiently low, electrons are excited upon illumination and can tunnel from the MoS₂ floating gate to the WSe₂ channel (Fig. 3(c)). Consequently, more electrons are released from and holes become trapped in the MoS₂ floating gate, leading to an increase in I_SD at V_SD = +1 V. When the device was irradiated with light pulses with V_Gp = −15 V, I_SD returned to a value higher than the initial value in the dark at V_G = 0 V, supporting that photoexcited electrons can tunnel from the MoS₂ layer to the WSe₂ channel by illumination with light pulses and V_Gp = −15 V. Fig. 3(d) shows I_SD measured at V_SD = +1 V when various values of V_Gp < 0 and 532 nm laser pulses with a width of 0.1 s and a power of 13 nW were simultaneously applied at the off state. I_SD increased stepwise even with V_Gp = −5 V, indicating that positive stepwise photoconductance can be obtained by the simultaneous application of small negative V_Gp and laser pulses. Moreover, these optoelectronic multilevel states were dependent on the laser power and wavelength (Fig. S3†).

Next, the device was switched to the on state at I_SD = +1 V by applying V_Gp = −50 V, which induced trapping of holes in the MoS₂ layer and led to n-type behaviors. Then, I_SD was measured at V_SD = +1 V, while a 532 nm laser was repeatedly turned on for 0.1 s and then turned off for 30 s (Fig. 3(e)). Interestingly, I_SD exhibited a stepwise decrease upon repeated exposure to laser pulses, and it decreased more rapidly with increasing laser power. This negative stepwise photoconductance can be explained by the tunneling of photoexcited electrons from the WSe₂ channel to the MoS₂ floating gate or the tunneling of holes from the MoS₂ floating gate to the WSe₂ channel, because the application of V_Gp = −50 V lowered the tunneling barrier to allow photoexcited electrons to tunnel from the WSe₂ to the MoS₂ (Fig. 3(f)). Similar measurements were performed upon repeated illumination with laser pulses with different exposure times and wavelengths (Fig. S4†). As the exposure time increased or the laser wavelength decreased, the I_SD decreased more rapidly owing to an increase in the number of photoexcited electrons.

To switch the device to the on state at V_SD < 0, V_Gp = +50 V was applied, which led to p-type behaviors. Upon repeated illumination with 635 nm laser pulses, the I_SD measured at V_SD = −1 V exhibited a stepwise negative photoconductance (Fig. S5(a)†). In this case, the tunneling barrier was lowered to allow photoexcited electrons to tunnel from the MoS₂ to the WSe₂ (Fig. S5(b)†); thus, illumination with laser pulses resulted in a decrease in |I_SD| at V_SD = −1 V. Although MoS₂ is nearly transparent, more photoexcited electrons might be created in the MoS₂ top layer than in the WSe₂ channel during irradiation. Thus, compared to the results with V_Gp = −50 V and V_SD = +1 V, a similar stepwise decrease in I_SD was obtained using laser pulses with a longer wavelength.

Application of rectifying optoelectronic memory devices to optoelectronic synapse devices

Fig. 4(a) shows the I_SD measured at V_SD = +1 V, when V_Gp = −10 V and 532 nm laser pulses (width of 1 s, power of 54 nW) were repeatedly and simultaneously applied after applying V_Gp = +50 V. I_SD exhibited 128 optoelectronic memory states. Subsequently, for depression, V_Gp = +11 V and 635 nm laser pulses with a width of 0.03 s and a power of 1 nW were simultaneously applied. Although I_SD was decreased by 532 nm laser pulses without V_Gp (Fig. 3(e)), more symmetric potentiation and depression curves could be obtained by the application of V_Gp = +11 V and 635 nm laser pulses. Fig. 4(b) shows the normalized conductance change (ΔS/S₀) measured at V_SD = +1 V after applying a 10-pulse train with an amplitude of −30 V and different spacing times (Δt) to V_G. As Δt decreased, ΔS/S₀ increased, implying that STDP can be realized using this device. We also performed theoretical learning and recognition tasks using an ANN with a size of 784 × 10 based on the SLP model. The recognition rate was estimated to be approximately 72%, which is comparable to the previously reported values (Fig. 4(e)).^38–40

Fig. 4 (a) I_SD measured at V_SD = +1 V for the WSe₂-based device with the MoS₂ top layer when V_Gp = +50 V was applied to switch the device to the off state and then, potentiation pulses (532 nm laser pulses (54 nW, 1 s) and V_Gp = −10 V) and depression pulses (635 nm laser pulses (1 nW, 0.03 s) and V_Gp = +11 V) were repeatedly applied. The insets show enlarged plots. Green and red dotted lines indicate the times when 532 nm and 635 nm laser pulses were applied, respectively, and the arrows indicate when V_Gp was applied. (b) Normalized conductance change (ΔS/S₀) measured at V_SD = +1 V after a 10 pulse train with an amplitude of −30 V and different spacing times (Δt) was applied to V_G, demonstrating spike-rate-dependent plasticity. (c) PSC measured according to number of pulses applied. The NL was estimated to be 0.5 and 4.2 for potentiation and depression, respectively. (d) Schematic of ANN model for analyzing post synaptic learning and recognizing processes of the device. (e) Recognition rate according to the number of learning processes.

In addition to the WSe₂/graphene device with the MoS₂ top layer, we fabricated a device with a WSe₂ top layer. It also exhibited gate-tunable rectification inversion, rectified nonvolatile memory properties, and multilevel optoelectronic memory effects (Fig. S6†). Furthermore, quite symmetric and linear potentiation and depression processes could be implemented using single-wavelength laser pulses with different powers (Fig. S7†). The NL was estimated to be 1.0 and 0.6 for potentiation and depression, respectively, which is more symmetric in comparison with the device with the MoS₂ top layer. These results suggest that the linearity and symmetry of the potentiation and depression curves may be improved by controlling the energy band structure.

Application of rectifying memory effects to mimicking excitatory and inhibitory synapses

The indicating that hole or electron tunneling can occur depending on the polarity of V_Gp suggests that this device may be applied to mimic excitatory and inhibitory synapses that involve different neurotransmitters. Glutamate is the most common neurotransmitter for excitatory synapses that brings the membrane potential of the postsynaptic neuron toward the threshold for generating action potentials, whereas GABA is the neurotransmitter for inhibitory synapses that drive the membrane potential of the postsynaptic neuron away from the threshold for generating action potentials.^41,42 To explore the feasibility of mimicking excitatory and inhibitory synapses, two similar devices were connected in parallel, as shown in Fig. 5(a). When V_Gp = −60 or +60 V was applied to both devices, the I–V curves showed rectifying characteristics with increasing current (Fig. S8(a) and (b)†). However, when V_Gp = −60 V was applied to one device and V_Gp = +60 V to the other device, the I–V curve was almost symmetric (Fig. S8(c)†).

Fig. 5 (a) A circuit consisting of two devices (A and B) connected in parallel (top) and a schematic of excitatory and inhibitory synapses connected to a postneuron (bottom). I measured at V of ±1 V square waves with a frequency of 5 Hz when V_Gp = −60 V was applied to device A, followed by repeatedly applying (b) V_Gp = −40 V or (c) V_Gp = +40 V to device B.

Fig. 5(b) and (c) show I measured at V of ±1 V square waves when V_Gp = −60 V was applied to device A, followed by repeatedly applying V_Gp = −40 and +40 V for 0.1 s to device B, respectively. Upon the application of V_Gp = −60 V to device A, rectified I was measured and its value was nearly unchanged due to the nonvolatile memory effects. Subsequently, when V_Gp = −40 V was repeatedly applied to device B, I gradually increased and the rectifying characteristics were maintained. In contrast, when V_Gp = +40 V was repeatedly applied to device B, I gradually decreased. We also performed similar measurements, in which V_Gp = +60 V was applied to device A and then V_Gp = −40 or +40 V was repeatedly applied to device B. Similar behaviors were observed although the polarity of I was changed (Fig. S9(a) and (b)†). These results demonstrate that the application of V_Gp = −40 and +40 V causes effects similar to activating excitatory and inhibitory synapses, respectively.

Conclusions

We fabricated WSe₂/graphene heterostructures with a photoresponsive floating gate of MoS₂ or WSe₂, and investigated their multifunctional properties including gate-controlled rectification inversion, rectified nonvolatile memory effects with an on/off ratio of 10⁴ and a retention time >10³ s, and multilevel optoelectronic memory effects. When V_Gp ≪ 0 was applied, the device was switched to the on state at V_SD > 0 and the off state at V_SD < 0 as electrons were trapped in the floating gate. In contrast, when V_Gp ≫ 0 was applied, the device was switched to the off state at V_SD > 0 and to the on state at V_SD < 0 as holes were trapped in the floating gate. Furthermore, upon repeated illumination with laser pulses, I_SD decreased or increased stepwise depending on the history of V_Gp, which was ascribed to the tunneling of photoexcited electrons between the WSe₂ channel and the floating gate through the hBN layer via the Fowler–Nordheim tunneling mechanism. In particular, 128 optoelectronic memory states with the NL < 1 could be achieved, suggesting that these multifunctional devices can be applied to optoelectronic synapse devices. Learning and recognition tasks were also performed using the ANN based on SLP model and the recognition rate was calculated to be approximately 72%. In addition, we demonstrated that WSe₂/graphene heterostructures with a floating gate may be applied to artificial synaptic devices that emulate inhibitory as well as excitatory synapses.

Experimental section

Device fabrication

Devices were fabricated, as shown in Fig. S10.† First, hBN flakes (15–21 nm) were mechanically exfoliated from an hBN single crystal (HQ graphene) using scotch tape and a selected hBN flake (∼11 nm) was transferred onto a SiO₂/Si substrate using a polydimethylsiloxane (PDMS) stamping method. The Au electrode (50 nm) was fabricated using electron-beam lithography and lift-off techniques and the graphene electrode (∼15 nm) was made by transferring a graphene flake (HQ graphene) onto the hBN. Next, a WSe₂ flake (∼10 nm) was transferred onto the prepared electrodes, resulting in a WSe₂ field-effect transistor (FET). After heating at 85 °C for 30 min on a hot plate, the FET was characterized. Subsequently, hBN (∼11 nm) and MoS₂ (∼11 nm) flakes were transferred onto the WSe₂ FET, and polystyrene was spin-coated to improve the contact between the vdW materials. WSe₂ and MoS₂ flakes were exfoliated from commercially available crystals (2D semiconductors).

Measurements

To characterize their optoelectronic properties, the devices were placed in a homemade vacuum chamber with an optical window. Electrical measurements were carried out using a semiconductor characterizer (4200-SCS, Keithley). Laser pulses were applied through the optical window and the exposure time was controlled using an optical shutter (SB5/M Aperture and SC10 controller, Thorlabs). SKPM images were acquired using an atomic force microscope (Park NX10, Park System) with a Cr–Au conducting cantilever.

Weight update method

A large-scale neural network with a size of 784 × 10 were constructed theoretically based on the single-layer perceptron model. The hand-written images of the MNIST database were pixelated with 255 levels of black and white contrast and then input as a form of a voltage matrix (V₁ − V_i, V). This input voltage was multiplied by a synaptic weight vector (W_1,1 − W_i,j, W) to be converted to an output current vector (I₁ − I_j = ∑V_i × W_ij). Here, the synaptic weight refers to the difference (W = G⁺ − G⁻) between the conductance state of potentiation (G⁺) and depression (G⁻) regions of the LTP/LTD curve. Next, the net current (net_j) collected at the output neuron was converted using the sigmoid function (ƒ(net_j)) to have values between “0” and “1”. The ƒ(net_j) was then subtracted to a label value (k_j) to define the weight-update determining factor ‘δ_j’ (δ_j = k_j − ƒ(net_j)). Finally using a sign function, when sgn(δ_j × V_i) was positive, we increased the synaptic weight between i_th input neuron and j_th output neuron and decreased the corresponding synaptic weights when sgn(δ_j × V_i) was negative. Finally, weight update was not processed when sgn(δ_j × V_i) is 0.

Author contributions

S. H. Kim proposed the idea, design the experiments and wrote the manuscript, M. U. Park, C. J. Lee and S. G. Yi helped perform electric and optical measurements, M. Kim helped optimize the scheme and figures and Y. Choi performed the SLP simulation.

Conflicts of interest

There are no conflicts to declare.

Acknowledgements

This work has been financially supported by the Basic Science Research Program through the National Research Foundation of Korea (NRF) (Grant No. 2019R1H1A2080077 and 2020R1A202011942).

Notes and references

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Footnote

† Electronic supplementary information (ESI) available. See DOI: 10.1039/d1na00504a

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