Challenges and opportunities in engineering next-generation 3D microelectronic devices: improved performance and higher integration density

Abstract

In recent years, nanotechnology and materials science have evolved and matured, making it increasingly easier to design and fabricate next-generation 3D microelectronics. The process has changed drastically from traditional 2D microelectronics, resulting in improved performance, higher integration density, and new functionalities. As applications become more complex and power-intensive, this technology can address the demands of high-performance computing, advanced sensors, and cutting-edge communication systems via wearable, flexible devices, etc. To manufacture higher-density microelectronics, recent advances in the fabrication of such 3D devices are discussed. Furthermore, the paper stresses the importance of novel materials and architectures, such as monolithic 3D integration and heterogeneous integration, in overcoming these challenges. We emphasize the importance of addressing complex issues to achieve better performance and higher integration density, which will play an important role in shaping the next generation of microelectronic devices. The multifaceted challenges involved in developing next-generation 3D microelectronic devices are also highlighted.

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1 Introduction

Miniaturized three-dimensional (3D) microelectronic devices made of advanced materials are expected to significantly impact various consumer and military applications in the near future.^1–3 These include energy storage/harvesting, photonic sensing, wearable electronics, biomedical technologies,^4,5 micro/nanoelectromechanical systems (MEMS/NEMS),^6,7 and high-performance transistors, to name a few.^8,9 For example, the currently used structure of Fin-FETs (tri-gate) transistors, which evolved from the traditional planar design, needs to advance further towards structures with gate-all-around (GAA) in 3D.^10–12 Using such advanced 3D structures enables higher functional density, higher performance, and less power consumption.^13,14 New R&D innovations in 3D transistors through advanced manufacturing and processing technologies is believed to enrich the future microelectronics industry.^15–18 Another illustration is the demand for next-generation chips and dense integrated circuits (ICs), which are required to perform a wider range of functions more extensively.¹⁹ This is especially desired beyond the technologies currently achievable through a simple lithography scaling method based on a single chip (system-on-chip).^20,21 To this end, researchers and engineers are working on technologies dealing with heterogeneous integrations in 3D architecture, including 3D IC packaging, 3D IC integration, and 3D Si integration.^22,23 3D IC integration is considered superior to 3D IC packaging as it allows stacking of much thinner IC chips with through-silicon-via (TSV) technology and micro-bumps. This architecture enables energy-efficient technology that offers higher integration, covers small areas, and performs better.²⁴

These numerous advantages of 3D devices and systems are poised to drive the development of next-generation microelectronics and photonics^25–27 and offer superior benefits: light weight, enhanced functional performance, energy efficiency, a smaller footprint, and cost-effectiveness compared to the existing planar 2D devices.^28,29 3D microelectronic devices also offer a high degree of integration and productivity.^30,31 Despite the advances that have been made, critical manufacturing technical challenges remain to be solved, especially in batch manufacturing, including thermal management, via formation, and thin-wafer handling.^30,32 In addition, devices with more complex 3D geometries, including conical spirals and hemispherical and polyhedral shapes, would be needed in future technologies.^33–35 These complex 3D architectures require advanced manufacturing processes for optimum performance.^36,37 Quantum computing is still in its infancy and is an exciting area within 3D microelectronics (Fig. 1).^38–40

Fig. 1 Next-generation 3D microelectronic devices are evolving rapidly, offering numerous opportunities in various industries.

Engineers are working on developing the hardware components and architectures required for quantum computers, which have the potential to revolutionize computing. 3D microelectronic devices, including implantable devices, diagnostics, and drug delivery systems, have significant medical potential.^41–43 The Internet of Things (IoT) relies on small, low-power devices that can be integrated into everyday objects. Engineers can work on developing 3D microelectronics that meet the stringent requirements of IoT applications, such as small size, low power consumption, and wireless connectivity.^44–46 With the growing demand for machine learning and artificial intelligence, there are opportunities to design specialized hardware for these applications. This can include neuromorphic computing and specialized AI accelerators.^47–49 As with all technological advancements, sustainability is an important consideration. Engineers are looking forward to developing a new eco-friendly class that can work on developing eco-friendly materials and manufacturing processes to reduce the environmental impact of 3D microelectronics.^{47,48,50–52} With the increasing connectivity of devices, security is a paramount concern. Engineers and researchers in this field play a crucial role in shaping the future of electronics, computing, and many other industries.^53,54 Several fabrication steps and intricate designs are involved in 3D microelectronic devices, which are smaller, faster, more powerful, and more energy-efficient than conventional electronics.^55,56

Fig. 2 is significant to researchers, industry experts, and decision-makers alike, encouraging collaboration and accelerating progress in next-generation 3D microelectronic devices. The increasing number of publications on these devices year by year and country by country demonstrates their importance. The next generation of 3D microelectronic devices could revolutionize a wide range of industrial areas. Engineers and researchers in this field play a crucial role in shaping the future of electronics, computing, and many other industries.

Fig. 2 Research papers published on next-generation 3D microelectronic devices [i] year-wise, [ii] country-wise and [iii] area-wise.

Several new materials have emerged and gained attention in 3D microelectronic devices. These materials are unique in their ability to meet semiconductor technology demands.^57,58 A glimpse of the state-of-the-art materials is given as follows:

(1) Ultra-low dielectric constants can reduce signal propagation delays and crosstalk in high-speed interconnects. Research is being conducted on organosilicates (SiCOH), porous silica, and organic polymers.

(2) A high-k dielectric has replaced silicon dioxide gate insulators in advanced transistors, allowing further device scaling and improved electrostatic control. For high-k gate dielectrics, hafnium oxide (HfO₂) and zirconium oxide (ZrO₂) are being investigated.

(3) Semiconductors made of InP and GaN have superior electron mobility. High-frequency and high-power applications use silicon-based platforms.

(4) Because of their nanoscale thickness, two-dimensional (2D) materials like graphene and TMDs have unique electronic and optical properties. Sensors, transistors, and interconnects are being investigated to enhance performance, increase flexibility, and save energy.

(5) Chalcogenide compounds (e.g., GeSbTe) are commonly used as phase change materials (PCMs) in non-volatile memories (PCMs). Due to reversible phase transitions, PCMs are ideal for non-volatile storage and high-speed switching.

(6) MOFs are porous materials composed of metal ions or clusters connected by organic ligands. Microelectronic devices are used for gas sensing, catalysis, and energy storage because of their high surface area, tunable pore size, and varied functionality.

(7) Flexible substrates, such as polyimide and PET, are required for wearable electronic devices. These materials allow electronic components to be integrated into flexible or curved surfaces in healthcare and consumer electronics.

Researchers are developing these materials to enhance the efficiency, performance, and functionality of microelectronic devices across a wide range of applications.

2 Manufacturing technologies for developing 3D microelectronic devices

Researchers have shown various manufacturing methods for 3D microelectronic devices comprising different structural and functional features.^32,59 Various manufacturing technologies are used to manufacture 3D microelectronic devices [Fig. 3].

Fig. 3 Various manufacturing technologies for developing 3D microelectronic devices.

These manufacturing methods mainly include micro-manufacturing and machining, mechanically guided 3D assembly approaches, and self-assembly processes. New techniques that include hybrid strategies are also being explored.^59–61 3D microelectronic structures featuring simple designs yield suspended and stacked components that can be fabricated relatively directly through modern micro-manufacturing technologies, including lithographic patterning, etching, and deposition.^62–64 On the other hand, methods based on mechanically guided 3D assembly can be employed as mature planar processing techniques available in the semiconductor industries to fabricate 2D precursor structures.^65–68 These 2D structures are subsequently processed into well-defined 3D forms by leveraging mechanically guided forces, including capillary forces, residual stresses, and constraint forces on inactive materials.^69,70 Many possibilities remain for improving and expanding existing manufacturing technologies.⁷¹ For example, futuristic manufacturing will aim to develop a universal method for deterministically controlling and forming 3D microelectronic devices with very high geometric complexity and ultra-small-scale precision.^32,72,73

In recent years, several fields, including semiconductors, have rapidly advanced in 3D and heterogeneous integration. This involves various techniques such as through-silicon via (TSV) interposer-based integration, fan-out wafer-level packaging (FOWLP), chip-on-chip, system-on-package (SoP), 2.5D and 3D circuits, monolithic 3D integration, and wafer-to-wafer bonding.^74,75 The TSV approach stacks multiple silicon wafers vertically with vertical interconnects running through the silicon substrate, resulting in shorter interconnects, smaller footprints, and better performance. Silicon substrates with high-density interconnects act as interposers, combining different semiconductor components like memory, logic, and sensors into one package. FOWLP allows the incorporation of multiple chips into a single package by redistributing the connection points, achieving size reduction, increased input/output density, and improved electrical performance.⁷⁶

Chips are stacked on each other, often using TSVs or micro bumps to connect them. CoC integration integrates logic and memory. Multichip SoPs include processors, memory, and sensors together in one package. The result is a highly integrated system that is highly efficient and performs well. The 2.5D and 3D IC integration approaches involve stacking multiple dies or wafers with interconnects. Die connections are made using interposers in 2.5D ICs, while multiple dies are stacked directly in 3D ICs.^77,78 In monolithic 3D integration, heterogeneous components are densely integrated with vertical connectivity. Multi-die integration is accomplished through W2W bonding, using TSVs or micro bumps to link multiple wafers vertically.⁷⁹

This integration structure and approach are continuously improving, becoming more compact, and enabling new capabilities in computing, networking, automotive, and consumer electronics.

2.1 Manufacturing routes involving micromachining processes

Various micro-manufacturing technologies employing top–down and bottom–up micromachining approaches, including selective etching, photoresist, wire bonding, and thinning processes, are shown in Fig. 4. In the microelectronics industry, several micromachining technologies have been employed, including laser and focused ion beam machining, deep reactive ion etching (DRIE), hot embossing, and bulk/surface micromachining.^88,89 Bulk or surface micromachining and DRIE methods have attracted much attention and are widely used in microelectronics industries.⁹⁰ Selective removal of the substrate material by chemical or physical means involves bulk micromachining to obtain 3D components.^91,92 In contrast, surface micromachining techniques can achieve more precise dimensional and structural control.⁹³ These techniques involve step-by-step deposition and patterning of sacrificial and structural layers, followed by the selective removal of the underlying sacrificial layer.²⁴

Fig. 4 (a) A schematic presentation shows a top-down 3D cantilever fabrication enabled by the etching of the sacrificial layer and a corresponding SEM image of a 3D MEMS mirror.⁸⁰ (b) Fabrication of nanowire ‘NW’ resonator arrays by a bottom-up integration process.⁸¹ (c and d) Schematic illustrations showing the fabrication process and a corresponding SEM image of 3D stacked gate-all-around ‘GAA’ transistors. GAA transistors are fabricated by selective etching of sacrificial layers and alternating etching-passivation steps [reproduced with permission from ref. 82. Copyright, Elsevier, 2020]. (e–g) 3D integration technology (three types) is displayed along with representative images.⁸³ (e) Stacked-die with wire bonding and package-on-package stacking, (f) memory stacking with through-silicon-via ‘TSVs’ [reproduced with permission from ref. 84. Copyright, Elsevier, 2020] and (g) wafer-to-wafer bonding⁸⁵ [reproduced with permission from ref. 86. Copyright, Elsevier, 2011].⁸⁷

The researchers initially developed a top–down approach for building 3D MEMS devices. DRIE was employed to fabricate 3D MEMS with high aspect-ratio features.^94,95 This was achieved by alternately etching Si and depositing etch-resistant material on the sidewalls. This technique is considered a cost-effective process that offers precision and can be extended to different materials, including silicon carbide, titanium, tungsten, glass, and polymers.^96,97 Furthermore, it has been shown that for manufacturing 3D MEMS with diverse suspension geometries, a viable approach is to combine various micromachining technologies to utilize the features of each technology.²⁴

On the other hand, building smaller units involving atoms and molecules into more complex assemblies based on their chemical properties needs bottom–up micromachining approaches.^98–100 This also represents a well-known manufacturing approach for self-assembling various morphological functional nanomaterials. Researchers have demonstrated combining bottom–up nanomaterials with micromachining technologies as an effective integration strategy that can facilitate the fabrication of 3D nanodevices.^101–103 These bottom–up integration processes were employed to fabricate nanowire ‘NW’ resonator arrays.^104,105

Microgeneration technologies aid in efficiently managing energy resources, which is essential for a long-term future¹⁰⁶. Variable design control compensates for the frameworks' restrictions by employing switches based on current utilization and energy supply accessibility.¹⁰⁷ A tiny battery capacity crossover energy arrangement is introduced. Using the collective energy of frameworks to meet electrical demands, reducing the dependence on the adjacent electricity company is possible.^108,109 Three alternative ways to control the system were compared, and the nonlinear reversal-based control scheme performed admirably. 3D microelectronic devices with highly varied structural and functional properties have led to the development of many manufacturing methods.³² Recent studies have extended this discovery to a broader range of materials (such as silicon carbide, titanium, tungsten, glass, and polymers), demonstrating a cost-effective method for deep drawing with excellent selectivity and accuracy.^110,111 The tension between the top and base layers, controlled by the substantial manufacturing boundaries, promotes the self-movement of 2D structures into deterministic 3D designs after the specific scratching of the sacrificial layer.^112–115 The framed devices could include several 3D practical pieces across various length scales to coordinate several functionalities into a single framework.^112–115

Rechargeable micro-batteries are critical power sources for microelectronic devices.^116,117 Two crucial goals for such devices are high energy output and a minimal footprint. Device configurations are crucial for improving output energy and reducing footprint size. We examine the progress made in folded-up nanotechnology, a descendant of origami technology, in manufacturing micro-batteries.¹¹⁸ On-chip electronic devices can readily incorporate three-dimensional sandwiched rMBs. The thickness of the electrode materials and the rMB's output energy are limited due to the sandwiched structure.¹¹⁹ The energy density can be enhanced by transitioning from a sandwich to an interdigital architecture.^120,121 A common packaging option is to deposit polymer flexible and wearable substrates. Solid-state electrolytes, such as LiPON, can overcome the leakage problem, but their electrical conductivity is low, limiting the ability of rMBs to store energy. On the other hand, polymer-based electrolytes can achieve a good balance between high conductivity and operational stability.^122,123

2.2 Mechanically guided 3D microelectronics assembly

Mechanically assisted manufacturing is a different method for creating 3D microelectronic devices capable of constructing complicated 3D geometries.^124–126 This method can be used to create multilayer and even hierarchical architectures. It can be used on various materials, including semiconductors, metals, polymers, and ceramics, and at various length scales, from tens of nanometers to centimeters. It is compatible with the semiconductor and integrated photonic industries.^127,128

The main characteristic of mechanically guided 3D assembly is different mechanical forces, including compressive forces due to a soft substrate, capillary forces, residual stress, and constraint forces (heat-, light-, and solvent-responsive active materials).¹²⁹ This technology's main step is deliberately distorting 2D precursor structures into 3D shapes. The main methods for accomplishing this include bending, twisting, or a combination of both.^130,131 Several mechanically guided 3D microelectronic assembly procedures are schematically illustrated in Fig. 5, along with a few manufactured 3D devices. The steps involve a residual stress method used to fabricate characteristic tubular or helical 3D electronic devices at an ultra-small scale.^136,137 Subsequently, the self-rolling of 2D precursors results in the deterministic 3D structures obtained after the sacrificial layer's selective etching.¹²⁹ Researchers have demonstrated several 3D electronic device prototypes using mechanically guided assembly.^138,139 The 3D devices that were fabricated include rolled-up field-effect transistors, 3D tubular infrared photodetectors with a widened visual field, and 3D radio frequency (RF)/microwave air-core transformers with enhanced performance compared to their on-chip planar counterparts.^140–142 Despite the advancements, it is important to note that the challenge of achieving the heterogeneous integration of multiple electronic components (e.g., ICs) at different in-plane locations remains.¹⁴³

Fig. 5 (a) Schematic presentation of an application to lithium-ion batteries due to residual stress-induced rolling [reproduced with permission from ref. 132. Copyright, Wiley 2013]. (b) An application in 3D deployable organic thin-film transistors (OTFTs) fabricated by the folding-dominated method [reproduced with permission from ref. 133. Copyright, Wiley 2014]. (c) An example of a representative microelectronic device with optically active split-ring resonator (SRRs) patterns is made by the induced folding-dominated method [reproduced with permission from ref. 134. Copyright, Wiley 2011]. (d) 3D photodetection systems that are capable of measuring incident light parameters developed by mechanically guided 3D assembly induced by compressive forces and a pre-strained substrate.^85,87,135

Daniel Karnaushenko et al.¹⁴⁴ discussed modern microelectronic systems and their components as predominantly three-dimensional (3D) devices that have decreased in size and weight to increase performance and reduce costs. Microelectronics has changed dramatically during the previous half-century in components and fully integrated systems. The rising compatibility defines the commencement of fully parallel wafer-scale production of 3D self-assembled microelectronic systems among multiple technologies and innovative materials.^145,146 Deviations and inaccuracies in the structure and design continue to pose challenges that affect device yield. They can only be overcome by fine-tuning material characteristics and manufacturing methods, which will undoubtedly incorporate self-stabilizing technologies.^147–149 Although 3D self-assembled microelectronics is still in its early stages, powerful prototype devices have already paved the road for integration into commercially accessible microelectronic systems and used in real-world applications.^150–152 System-on-Package (SoP) technology based on silicon carriers can support robust chip manufacturing with high-yield/low-cost chips for various products of two- and three-dimensional product applications.¹⁵³ It can also provide modular design flexibility and high-performance integration of heterogeneous chip technologies.^154–156 The silicon carrier package's thermal expansion matches that of the chip, ensuring dependability even when the high-density chip micro-bump interconnections shrink in size.^157,158 This method appears to scale with semiconductor advancements in electrical, thermal, and I/O scaling.¹⁵⁹ It will also assist in directing technology toward product applications that demonstrate the highest cost-effectiveness. The integration of silicon and packaging using new 2D and 3D structures is fascinating for supporting system requirements and new volume-based product applications.^160–162

2.3 Compact 3D self-assembled microelectronics

A new area of research, 3D self-assembled microelectronic devices, is anticipated to simplify production procedures and offer unique functions in the microelectronics industry of the future.^163,164 Creating sophisticated 3D architectures from initially planar membranes is quickly becoming possible, which is a very effective method for producing 3D electronics.^165,166 Because it presents new prospects to integrate thin-film microelectronic functions in systems and devices with increased performance and higher integration density, 3D self-assembly has demonstrated its significant advantage in recent research. To optimize self-assembled 3D architectures, researchers have worked on resolving chemistry, structural stability, and yield problems and devising novel techniques.^167,168 Different 3D structures have been created using self-assembly techniques. Complex thin-film electrode architectures, 3D self-assembled passive and active components, as well as sensor, mechanical, and energy supply devices have all been successfully integrated (Fig. 6).¹⁴⁴

Fig. 6 Schematic illustrations show three distinct driving mechanisms: surface tension, extrinsic forces, and intrinsic interfacial and volumetric stresses that can be leveraged to fabricate 3D self-assembled microelectronic devices wafer-scale-processable and deployable.¹⁴⁴

The underlying mechanism of 3D self-assembly works parallelly, taking advantage of surface tension, extrinsic forces, and intrinsic interfacial and volumetric stresses.^169–171 For example, it has been shown that in the case of reorienting conventional MEMS and NEMS structures, positioning microelectronic components, and fabricating polyhedral architectures, the surface tension of various materials in the liquid phase plays a crucial role and has been extensively utilized.³⁰ Similarly, extrinsic forces can be leveraged for structural buckling, which was utilized to form diverse pop-up 3D architectures.¹⁷² In another example, rolled-up tubular and “Swiss-roll” architectures were created by applying intrinsic interfacial or volumetric stresses.^173,174

Microelectronics that are self-assembled have several intriguing possibilities. The most critical component is the 3D shape's compactness, which immediately enhances the form factor.¹⁷⁵ As a result, energy storage components like batteries, capacitors, and inductors perform better per footprint area. This has also been demonstrated to offer novel properties for magnetic sensors missing from the initial planar state.^176,177 According to research, 3D optical and electrical devices are employed as mechanical scaffolds to examine, work with, and interact with biological fluids and soft tissues.¹⁷⁸ 3D self-assembled microelectronics is still a nascent and developing field. But it is anticipated that potent prototype devices which have already been revealed could open the door to the microelectronics commercialization industry for useful applications.¹⁴⁴

2.3.1 Hybrid manufacturing technologies to realize 3D multifunctional microelectronics. Recent research suggests that combining various technologies can circumvent some technological constraints imposed by micro-manufacturing and self-assembly approaches.^61,179 For instance, scientists have used 3D IC integration technology to create an interposer (carrier) micro-device. For thermal control, this microdevice integrates fluidic microchannels made using wet etching (Fig. 7). The development of TSV-based 3D integration for the chip-scale package of MEMS and ICs was demonstrated using micromachining technology.^183,184 From an industrial standpoint, the heterogeneous integration of many functional components, such as logic processors, RF devices, biochips, sensors, and MEMS, into a single chip can be revolutionary in providing affordable and value-added system solutions.^185,186

Fig. 7 Formation of 3D multifunctional microelectronics devices by hybrid manufacturing/assembly methods.²¹⁷ (a) Schematic illustration showing an interposer (carrier) device with fluidic microchannels for thermal management.¹⁸⁰ (b) Chip-scale integrated MEMS and ICs.²¹³ (c) Mechanically guided 3D assembly assisted by residual stresses [reproduced with permission from ref. 181. Copyright, Wiley 2017]. (d) The combination of mechanically guided 3D assembly and residual plastic deformations of metals results in freestanding 3D structures.¹⁸² (e) Merging of micro-manufacturing technologies and other mechanically guided 3D assembly methods with 3D assembly based on compressive buckling.²¹⁵

Advanced 3D microelectronic packaging technology is currently very useful in meeting the requirements of portable electronics and heterogeneous integration roadmaps due to its ultra-thin and ultra-light design, good performance, and low power consumption.^187,188 Another significant benefit is that it adheres to Moore's law at a much cheaper cost compared to the semiconductor industry.^189,190 Various facets of 3D packaging have also been investigated, including manufacturing, assembly, cost, design, modeling, heat management, material, etc.^191,192 Three-dimensional hyper integration is a revolutionary technique for building highly integrated micro–nano systems by vertically stacking and connecting numerous materials, technologies, and functional components.^193,194 Memory, handheld devices, and high-performance computers will lead to high-density multifunctional heterogeneous integration of InfoTech, NanoTech-BioTech systems.^195,196 The government, public, and private investors have invested heavily in developing stacked 3D silicon for years. This technology is mass-produced and stacked with 3D silicon components, and product designers can use foundry services. Stacked 3D silicon has already made a big difference in the microelectronics systems and products in which it is used.^197,198 Due to the presence of multiple gates, multi-gate FETs are a better option than planar MOSFETs for drain potential screening from channel.¹¹⁰ FinFET devices have reduced fringing capacitances but that come with higher fabrication costs.^199–201 They consume less power, are immune to SCEs, take up less space, and function faster.²⁰² The most recent advancements in FinFET technology are examined by addressing circuit and manufacturing issues and different FinFET structures, such as SOI MOSFETs and SOI NERFETs.²⁰²

New wireless technologies, including new usage patterns and protocols, transform our daily lives.^203,204 The heterogeneous functionality required for expanding consumer, communication, and defense microsystems cannot be combined into a platform based on semiconductor device scaling because the convergence of communication, computing, optical, and sensing technologies necessitates complete system implementation on ultra-small form factor mobile platforms.²⁰⁵ It is possible to increase system-level performance, reduce form-factor, and lower power dissipation by utilizing 3D integration of low-power, highly efficient, process-optimized IC and packaging technologies.^205,206 The desire for multifunction mobile platform-based designs drives the demand for 3D integration of heterogeneous technologies. Monolithic 3D-ICs, stacked 3DICs, and POPs only make up a minor portion of a platform's overall system.^207,208 The multifunction system must be reduced before the full advantages of 3D integration can be realized. Although there are significant challenges associated with 3D integration for wireless mobile internet and computer platforms, it also creates new opportunities for system architecture, design, integration, manufacturing, and testing.^209–211 Electronic connection and packing chores are typically carried out in 2D. To further miniaturize and enhance the functionality of electronic devices, 3D integration is required.^212,213 The desire for multifunction mobile platform-based designs drives the demand for 3D integration of heterogeneous technologies. With its ultra-thin and ultra-light design, and excellent performance while consuming very little power, advanced 3D microelectronic packaging technology is currently beneficial in achieving the demands of portable electronics and heterogeneous integration roadmaps.²¹⁴ It adheres to Moore's law at a much lower cost compared to the semiconductor industry, which is another noteworthy advantage. Many other aspects of 3D packaging were explored, including fabrication, assembly, cost, design, modeling, heat management, material, and many more.^215,216

A mechanical-materials-and-reliability engineer will probably have to deal with problems related to exciting developing technologies in numerous fields.^215,216 Unless something unexpected disrupts the current trend and defines the near future, predicting future technology is not as difficult as it initially appears. This happens due to the sudden change in momentum of these movements. Continuous innovation is required to meet the future demands of electrical and photonic technologies.²¹⁴ The fundamental problem is that silicon chips have limitations when it comes to integrating photonic capabilities, even though they enable our CPUs, computer memory, communication processors, and image sensors.^217–219 Hence, a layer is used to construct optical waveguides to overcome this challenge and integrate photonics into bulk silicon complementary metal-oxide-semiconductor devices.^220,221 This transistor-based photonic device can achieve many of the multi-chip approach's objectives when decoupled.

3 Challenges and constraints in the fabrication of 3D microelectronic devices

Numerous constraints and challenges are associated with the fabrication of 3D microelectronic devices.^209,210 The following are some of the most important challenges and constraints in fabricating 3D microelectronic devices [Fig. 8].

Fig. 8 Various challenges and constraints in the fabrication of 3D Microelectronic Devices.

Due to the increased power density and limited thermal dissipation in compact, multilayered structures, 3D microelectronic devices pose significant challenges in heat management. Variations in thermal expansion among materials can lead to stress, delamination, cracking, or warping. Unmanaged hotspots from active components can degrade overall performance, while temperature fluctuations impact device reliability due to mechanical stress from large gradients. Moreover, issues such as electromigration, diffusion, and voids arising from high fabrication temperatures can weaken interconnects and solder joints. Selecting materials that effectively conduct heat and closely match in expansion rates is critical, although choices are often restricted by process compatibility and cost considerations. Additionally, integrating microfluidic cooling and heat sinks presents further complexities.

Using fabrication processes compatible with the materials is important, as excessive heat can damage components. Thermocycling and accelerated aging tests can be used to evaluate long-term reliability. Voltage scaling and power gating should be used to minimize heat generation. To maintain uniform temperatures across layers, heat must spread efficiently. Thermal restrictions can be addressed with advanced packaging designs, material choices, and thermal interface materials.

3.1 Thin film deposition and uniformity

The Through-Silicon Via (TSV) is integral to vertical interconnections in microelectronic devices but introduces a few challenges. Costs and cycle times increase when fabrication steps like etching, deposition, and planarization are added. TSVs must be precisely aligned to prevent electrical shorts, open circuits, or reduced performance. Having high aspect ratios makes etch depth control and sidewall uniformity difficult. In DRIE, the substrate can be damaged, affecting reliability. The TSVs can also cause thermal management issues and electromigration, resulting in voids and reduced reliability. The performance of devices can be affected by mechanical stresses during TSV fabrication. A thin wafer exposes TSVs, posing challenges in mechanical stability. Electrical leakage and crosstalk can occur when structures are densely packed, making proper dielectric isolation essential. It is crucial to test and characterize TSVs comprehensively. Conducting non-destructive testing to detect defects, such as voids or cracks, is crucial. Fabrication of TSVs increases manufacturing costs due to process complexity and the need for additional materials. The commercialization of 3D-integrated devices poses a significant challenge. Optimizing TSV fabrication, improving material properties, enhancing alignment techniques, and developing reliable testing methods require ongoing research. 3D microelectronics requires collaboration between semiconductor manufacturers, equipment providers, and research institutions.

3.2 Testing and reliability

Testing and reliability considerations are crucial for fabricating 3D microelectronic devices, ensuring that they meet performance specifications and maintain functionality throughout their operational lifetime. Access constraints and interconnect testing present challenges in evaluating the functionality and reliability of 3D microelectronic devices. Yield monitoring, non-destructive testing, and long-term stability testing are essential for ensuring the reliability of 3D microelectronic devices. Collaboration between device designers, process engineers, reliability engineers, and testing specialists is essential for implementing effective testing and reliability strategies and ensuring the quality and performance of 3D microelectronic devices.

3.3 Cost considerations

Material, equipment, and labor costs significantly impact fabrication expenses. Balancing testing requirements, R&D expenses, and packaging and assembly costs is crucial for cost-effective manufacturing. Cost constraints heavily influence the fabrication of 3D microelectronic devices, affecting manufacturing processes, material selection, equipment utilization, and overall production efficiency. Additionally, material waste and environmental compliance contribute to production costs. Strategies like recycling and sustainable practices help mitigate expenses. High-volume production lowers per-unit costs; however, initial setup costs and production ramp-up expenses should also be considered.

3.4 Integration of heterogeneous components

Integrating heterogeneous components in the fabrication of 3D microelectronic devices introduces several constraints and challenges stemming from differences in materials, processes, interfaces, and functionalities. Key considerations include material compatibility, process compatibility, dimensional mismatch, interfacial adhesion and bonding, thermal management, electrical interconnects, signal compatibility and interface design, reliability and durability, as well as testing and characterization. Addressing these constraints requires interdisciplinary collaboration among materials scientists, process engineers, device designers, and reliability experts to develop innovative integration techniques, materials compatibility guidelines, and testing methodologies tailored to the unique challenges of heterogeneous component integration in 3D microelectronic devices. Challenges include material and process compatibility. Issues like dimensional mismatches and thermal management must be addressed.

3.5 Environmental and sustainability constraints

The fabrication of 3D microelectronic devices presents several environmental and sustainability constraints that must be addressed to minimize environmental impact and promote sustainable manufacturing practices. Some key constraints in this regard are resource consumption, chemical usage and waste generation, emissions and air quality, water usage and contamination, energy consumption, and carbon footprint, waste generation and disposal, supply chain sustainability, product lifecycle management, regulatory compliance, corporate social responsibility. Addressing these environmental and sustainability constraints requires a holistic approach to manufacturing that integrates environmental considerations into all aspects of the production process, from materials sourcing and process design to waste management and product lifecycle management. Collaborative efforts among industry stakeholders, government agencies, academia, and environmental advocacy groups are essential for driving innovation and promoting sustainable practices in fabricating 3D microelectronic devices.

3.6 Process control and monitoring

Process control and monitoring are essential aspects of fabricating 3D microelectronic devices, ensuring consistent performance, quality, and reliability throughout manufacturing. However, several constraints and challenges like complexity of process flows, dimensional variability, material compatibility, alignment and registration accuracy, process variability and yield losses, equipment and tooling constraints, real-time monitoring challenges, data management and analysis, environmental and safety considerations are associated with process control and monitoring in this context. Addressing these constraints requires continuous improvement efforts, investment in advanced process control technologies, employee training, and collaboration among interdisciplinary engineers, scientists, and technicians. By overcoming these challenges, semiconductor manufacturers can enhance process control and monitoring capabilities, improve product quality and yield, and drive innovation in 3D. Challenges include complex process flows and dimensional variability. It is essential to monitor material compatibility, alignment accuracy, and process variability.

3.7 Scaling and miniaturization

Scaling and miniaturization in the fabrication of 3D microelectronic devices introduce several constraints and challenges, primarily due to the shrinking dimensions of device features and the increasing complexity of fabrication processes. Here are some key constraints: lithography limitations, aspect ratio limitations, material constraints, interconnect scaling, thermal constraints, manufacturability constraints, metrology and inspection challenges, cost constraints, reliability concerns, and design complexity are associated with scaling and miniaturization. Addressing these constraints requires interdisciplinary collaboration among device designers, process engineers, materials scientists, and equipment manufacturers to develop innovative solutions, optimize fabrication processes, and overcome technical challenges associated with scaling and miniaturization in 3D microelectronic device fabrication.

3.8 Standardization

Standardizing the fabrication of 3D microelectronic devices faces numerous constraints and challenges due to the technology's intricate and fast-evolving nature. Key issues include heterogeneous integration, customization, rapid technological advancements, interdisciplinary collaboration, global supply chain complexities, intellectual property protection, cost management, regulatory compliance, and the integration of legacy systems and technologies, all of which contribute to market fragmentation. Despite these challenges, standardization offers substantial benefits such as interoperability, compatibility, cost efficiencies, and accelerated innovation. Addressing these hurdles demands proactive stakeholder engagement, effective communication, consensus-building, and a dedicated effort towards collaborative problem-solving and ongoing enhancement.

3.9 Complexity in existing design tools

Design tools facilitate performance optimization, complexity management, and manufacturability. EDA software can be used for layout, simulation, and verification, as well as 3D integration and heterogeneous system design tools. FEA, FDM, and CFD may be used for thermal and mechanical analyses, along with electromagnetic simulation tools for signal integrity and electromagnetic interference (EMI). Through electrical and thermal co-design approaches, floorplans, partitions, and interconnects can all be optimized. Technology compatibility, accuracy, and scalability are possible issues. Multiphysics simulation capabilities may be integrated into design automation using machine learning and artificial intelligence.

4 Conclusion and future scope

This paper highlights the significant challenges in developing 3D microelectronic devices and the available opportunities. It emphasizes the enormous improvements in performance and integration density that these technologies promise while stressing the necessity for innovative solutions to overcome heat dissipation, material compatibility, and fabrication complexity to achieve these advancements. As a result of 3D integration, the paper emphasizes the importance of pushing the boundaries of microelectronic device performance. It advocates for a multidisciplinary approach that combines academia, industry, and research institutions to tackle the existing hurdles and advance the field.

Several promising directions are being pursued for the future of 3D microelectronic devices, such as the following. There is a growing need for research on new materials and advanced fabrication techniques to improve device performance and reliability. As densely packed 3D structures continue to become more complex, it will be crucial to address thermal management challenges with innovative solutions to ensure their sustainability. Aside from this, the exploration of new interconnect technologies and the improvement of design methodologies will allow for higher data rates and optimized performances to be achieved. We want to highlight that there is a wide range of potential applications of 3D microelectronics in emerging areas such as IoT, artificial intelligence, and quantum computing, and efforts should focus on making these technologies more sustainable and cost-effective to ensure their widespread adoption and impact across several industries.

Conflicts of interest

There are no conflicts to declare.

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