Optimized nano-scaled drain- and gate-engineered Schottky barrier MOSFET with improved ambipolarity and RF characteristics

Abstract

In this work, a novel Schottky Barrier MOSFET (SB-MOSFET) structure is presented. The proposed device consists of a dual-material gate and electrostatically doped drain, and the device is denoted as Gate and Drain Engineered Schottky Barrier MOSFET (GDE-SBMOSFET). The use of a dual-material gate and electrostatically doped drain enhances the ON state performance and short channel performance, respectively, in comparison to state-of-the-art devices. By optimizing the gate and drain metal workfunction, the proposed device technology node can be scaled below 22 nm without exhibiting performance degradation. The optimized values of the metal workfunction of the drain and tunnel gate (TG) improve the parameters, such as the ON current and ON/OFF current ratio, which have been increased 26- and 10-fold in comparison to conventional SBMOSFETs. Additionally, a substantial enhancement of 28% and 4% in the SS of the proposed GDE-SBMOSFET has been achieved in comparison to that of the DSL and conventional SB-MOSFET, respectively. The ac investigation has shown that the cut-off frequency (f_T) in the GDE-SBMOSFET (∼510 GHz) has increased 51 and 2 times as compared to that of the conventional SB-MOSFET (∼10 GHz). Further, the GDE-SBMOSFET has higher scalability and reduced ambipolarity, and doping-related issues caused by doped regions are absent in the proposed device.

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1. Introduction

The performance enhancement of MOSFETs depends heavily on their dimensions. Reducing the size of MOSFETs has led to significant advancements in terms of speed, packaging density, power dissipation, and cost. However, scaling these devices below 32 nm becomes challenging due to issues such as gate oxide tunneling, drain tunneling, doping-related problems, parasitic effects, and short channel effects (SCE).^1–3 Various methods have been proposed by researchers to address these challenges,^4–11 with ultra-thin junctions and heavily doped source/drain (S/D) regions being considered effective solutions. SB-MOSFETs (Schottky Barrier MOSFETs) combine these properties,¹² making them an essential approach to tackling SCEs and reducing large the RSD (source drain resistance). Moreover, SB-MOSFET offers additional benefits, including better control over off-state current, lower parasitic capacitance, increased channel mobility due to undoped channel doping, simpler and more cost-effective S/D realization process, scalability, rejection of parasitic bipolar effects, and a comparatively straightforward fabrication procedure.^13,14

In spite of these advantages, Schottky barriers have drawbacks. In the off-state, leakage current primarily occurs due to thermal emission, which requires a high Schottky barrier to suppress it. Conversely, a zero-height barrier is preferable for achieving significant on-current during the on-state. Therefore, there is always a trade-off between these two requirements. A low Schottky barrier improves the on-state tunneling current but reduces the I_ON/I_OFF ratio due to increased off-state leakage current.^15,16 Researchers have proposed different approaches for enhancing the I_ON/I_OFF ratio through the reduction of the Schottky barrier height. One successful method discussed in ref. 10, 17 and 18 involves employing a dopant segregation layer to modulate the barrier. However, this technique is laborious and increases the complexity and thermal requirements during device fabrication. Another proposed solution is the utilization of nano-scaled SB-MOSFETs, in which shorter spacer lengths are utilized to amplify the fringing fields on the barrier. This, in turn, improves the device's driving capability, as mentioned in ref. 19. Additionally, the performance of SB-MOSFETs can be improved by implementing an ultrathin silicon-on-insulator (SOI) substrate, which enhances the carrier injection capability of the SB, as demonstrated in ref. 20–22. An alternative approach presented in my previous work ^9,10 involves the use of an extended source, but its fabrication becomes considerably challenging at sub-10 nm scales. In addition to this, there is an ambipolarity issue in SB-FETs, which deteriorates the performance of the SB-FETs. Several studies have addressed this issue, and some solutions, such as 2D material-based devices, have been proposed in the literature.^23–26 However, the mass fabrication of 2D materials is still in its infancy.

This paper investigates the performance of a new type of SB-MOSFETs (Schottky Barrier MOSFETs) compared to that of conventional ones through a detailed comparative analysis. The proposed device utilizes a metal silicide (ErSi_1.4) in the source/drain region and an undoped silicon material in the channel. The use of silicides is advantageous, as they can be easily realized at low temperatures,²⁷ and their low resistance makes them appropriate for nodes of less than <10 nm. The proposed device incorporates gate and drain engineering, which enhances its resistance to SCEs (short channel effects). Furthermore, the top gate of the device uses two metal workfunctions and has a low metal workfunction gate near the source channel junction. Various performance parameters, including I_ON, I_ON/I_OFF, transconductance (g_m), and other analog/RF application parameters, have been calculated. The results indicate that the proposed device outperforms both conventional devices and the current state-of-the-art devices.

This paper is divided into four sections. Section II discusses device structures and simulation parameters of the conventional and the proposed devices. Section III discusses results. Section IV concludes the paper.

2. Structural description and simulation parameters

Atlas Silvaco TCAD²⁸ was used to carry out simulations of the conventional, DSL-SBMOSFET and proposed GDE-SBMOSFET device structure. For accurate comparative analysis, various models were used in the TCAD simulations, namely, srh, fermi, consrh, drift diffusion, conmob, fldmob and ust. The transport of carriers in the channel is mainly governed by the drift diffusion model. The tunneling across the metal semiconductor junction is captured by the Schottky tunneling model (ust), whereas conmob and fldmob mobility models were used to capture the field- and concentration-dependent mobility. In addition to this, the band-to-band tunneling model (BTBT) was used in the proposed device to check the tunneling at the drain channel interface.

The schematics of the conventional, dopant segregation layer (DSL) and proposed Gate and Drain Engineered (GDE) Schottky Barrier MOSFET devices studied in this work are shown in Fig. 1. In the calibration of the model, the device structure, including its dimensions and other parameters, remained consistent with those utilized in ref. 19 for generating simulation data. Fig. 1d demonstrates the remarkable agreement between the simulated results and the experimental data reported in ref. 19. In the proposed GDE-SBMOSFET structure, the drain has been realized electrostatically using the optimized metal workfunction and the gate consists of two types of material, denoted as the Tunnel Gate (TG) and Main Gate (MG). The TG has a low metal workfunction and is responsible for modulating the barrier width at the Source Channel interface in the proposed device. The summarized device design parameters for all the devices can be found in Table 1. Upon conducting a comprehensive analysis of the device, it is evident that the GDE-SB-MOSFET exhibits a noteworthy band bending effect.

Fig. 1 Schematics of (a) conventional SBMOSFET, (b) DSL SBMOSFET and (c) proposed GDE-SBMOSFET. (d) Model Calibration using experimental data. ¹⁹

Table 1 Structural parameters of proposed and conventional devices

Parameter	Conv. SBMOSFET	DSL-SBMOSFET	Proposed GDE-SBMOSFET
Gate length	20 nm	20 nm	20 nm
Oxide thickness	1 nm	1 nm	1 nm
Undoped Si thickness	8 nm	8 nm	8 nm
Length of device	100 nm	100 nm	100 nm
Gate work function	4.72 eV	4.72 eV	4.9 eV and 4.65 eV
DSL doping conc	NA	6 × 10^19 cm^−3	NA
Drain metal workfunction	4.5 eV	4.5 eV	3.9 eV
Source metal workfunction	4.5 eV	4.5 eV	4.5 eV
Width of tunnel gate	NA	NA	2 nm
Work of tunnel gate	NA	NA	3.7 eV
L Gap,Drain	NA	NA	4 nm

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3. Process flow for the GDE-SBMOSFET

This band bending plays a crucial role in enhancing various parameters such I_ON, I_ON/I_OFF ratio, SS, g_m, f_T and other related parameters.

The possible steps for the fabrication for the proposed GDESB-FET are shown in Fig. 2. The device would be fabricated on a lightly doped (10¹⁶ cm⁻³) p-type silicon substrate, followed by metal silicidation. In order to achieve precise control over depth and ensure high smoothness with less than 1 nm roughness on the vertical walls and edges, lithography was performed, followed by CF₄ plasma oxide etching at a temperature of −20 °C.²⁹ The deposition of the tunnel gate and main gate electrodes would be carried out using a metallization process. To lower the deposition temperature, a method called plasma-enhanced chemical vapor deposition (PECVD) would be employed. Alternatively, low-pressure chemical vapor deposition (LPCVD) could also be utilized to attain higher purity, uniformity, and reduced chemical contamination.^30,31

Fig. 2 Process flow of the proposed device.

4. Results and discussion

4.1. DC characteristics

The band diagrams (BD) of DSL-SBMOSFET and GDE-SB-MOSFET in the ON- and OFF-states are shown in Fig. 3.

Fig. 3 Energy band diagram of the conventional and proposed device in the (a) OFF state (V_DS = 0.5 V, V_GS = 0 V) and (b) ON state (V_DS = V_GS = 0.5 V).

It is clear from the Fig. 2 that barrier width at the source and channel interface has been modulated by using the DSL and tunnel gate (TG) in the DSL-SBMOSFET and GDE-SBMOSFET respectively, and the modulation of the barrier width is more effective in the GDE-SBMOSFET. Additionally, the barrier height in the channel is higher in the case of GDE-SBMOSFET; therefore, the proposed device is less susceptible to short channel effects compared to the DSL and Conventional SBMOSFET. The enhancement in performance characteristics of the GDE-SBMOSFET as compared to the conventional devices can be due to the efficient use of the electrostatically doped drain and gate engineering concepts.

Fig. 4 shows the effect of the drain metal workfunction on the energy bands and electron concentration in the GDE-SBMOSFET. It was observed that lowering the metal workfunction increases the electron concentration and lowers the energy bands. The device profile of the GDE-SBMOSFET for 3.9 eV drain metal workfunction is shown in Fig. 4(b), where the formation of charge plasma is visible.

Fig. 4 Proposed GDE-SBMOSFET: (a) energy bands with different drain metal workfunctions; (b) device profile; (c) electron concentration with and without biasing; (d) electron concentration with different drain metal workfunctions.

The device characteristics of all the device structures as calculated at V_DS = V_GS = 0.5 V are shown in Fig. 5. The I_ON of the GDE-SBMOSFET is 26 μA μm⁻¹, while those of the DSL-SBMOSFET and conventional SBMOSFET are 20 μA μm⁻¹ and 1 μA μm⁻¹, respectively. The I_ON/I_OFF ratio of the GDE-SBMOSFET (1 × 10⁴) is enhanced by about ∼100 and 10 times compared to those of the DSL-SBMOSFET (2 × 10²) and conventional SBMOSFET (1 × 10³) counterparts, respectively. This outstanding performance in the GDE-SBMOSFET can be attributed to the band bending in the channel of the GDE-SBMOSFET, as is evident from the EBD in Fig. 3. There is a 28% and 4% improvement in the subthreshold swing in the GDE-SBMOSFET (93 mV dec⁻¹) compared to that of the DSL-SBMOSFET (130 mV dec⁻¹) and conventional SBMOSFET (97 mV dec⁻¹).

Fig. 5 Transfer characteristics of GDE-SBMOSFET, DSL-SBMOSFET and conventional SBMOSFET.

Fig. 6 shows the ambipolarity behavior of all three devices under consideration. It was observed that GDE-SBMOSFET exhibits almost no ambipolar current; therefore, circuits designed using GDE-SBMOSFET can have low short-circuit power dissipation. The lower ambipolar conduction in the GDE-SBMOSFET can be attributed to the electrostatically designed drain in the GDE-SBMOSFET. The use of an optimized workfunction at the drain electrode controls the ambipolar current.

Fig. 6 Transfer characteristics showing ambipolar behavior in all three devices under study.

Fig. 7 shows the effect of the gate drain gap (L_Gap,Drain) and drain metal workfunction on the performance of the proposed device.

Fig. 7 Impact of (a) gate drain gap (L_Gap,Drain) and (b) drain metal workfunction (W.F_Drain) on the performance of the proposed device.

It was observed that as the gap and workfunction increase, the leakage decreases. The increase in the gap and workfunction widens the energy band at the drain channel interface and thus improves the leakage.

Fig. 8 shows the influence of the temperature on the transfer characteristics of the GDE-SBMOSFET and DSL-SBMOSFET. It was observed that the GDE-SBMOSFET shows a weak dependence in the ON state as compared to the conventional device. This weak dependence can be attributed to the tunnel gate and electrostatically doped drain. The charge concentration created beneath the tunnel gate varies with the depth, whereas the DSL shows constant variation with depth, which results in a variable Schottky barrier width in proposed device.

Fig. 8 Effect of temperature on (a) GDE-SBMOSFET (b) DSL-SBMOSFET.

4.2. AC analysis

Fig. 9 shows the plot of the cutoff frequency against the gate voltage at a constant drain voltage. It was found that a higher value of f_T was observed in GDE-SBMOSFET.

Fig. 9 Cutoff frequency (f_T) comparison of all three devices.

The higher value of f_T may be due to the higher transconductance and lower capacitance in the proposed device in comparison to the conventional devices. Fig. 10 shows the transconductance generation factor (g_m/I_D) of all three devices. It was observed that the g_m/I_D is higher in the GDE-SBMOSFET over the entire range of gate voltages.

Fig. 10 Transconductance generation factors of all three devices under study.

It was observed that the g_m/I_D of the proposed device was much higher for entire V_GS range. The higher value of g_m/I_D for the proposed device may be due to the higher driving and transconductance in the proposed device.

4.3. Impact of gate length scaling

The influence of different gate length dimensions on the performance-measuring parameters is shown in Fig. 11. The effect of the gate length on threshold voltage (V_th) and subthreshold swing (SS) of the GDE-SB-MOSFET and DSL-SB-MOSFET is shown in Fig. 10a. It was found that the GDE-SB-MOSFET technology node can be scaled well below 12 nm without any performance loss as compared to DSL-SB-MOSFET. The leakage current is significantly lower in GDE-SB-MOSFET as compared to DSL-SB-MOSFET for all gate lengths, as shown in Fig. 11b. Fig. 11c presents the variation in the cut-off frequency (f_T) and ON current with respect to gate length. Both the f_T and ON current are higher in the GDE-SB-MOSFET as compared to DSL-SB-MOSFET.

Fig. 11 Impact of gate length scaling on (a) threshold voltage, sub-threshold swing and (b) leakage current of the GDE-SBMOSFET and DSL-SBMOSFET.

It was observed that optimization of the drain metal workfunction and tunnel gate metal workfunction played a major role in obtaining significantly improved performance in the measured parameters of the GDE-SB-MOSFET.

The performance of the proposed device was compared with those reported in the previously published works on SB-MOSFETs and is summarized in Table 2. From the table, it can be seen that the proposed device presents comparatively very good performance considering the employed gate length and supply voltages. Additionally, the proposed device suppresses the ambipolar current, which is an important concern with SB-MOSFETs. The ambipolarity issue was not addressed by most of the works presented in the table.

Table 2 Comparison of our work with the previously published works

Ref.	L G (nm)	V DS/VGS (V/V)	f T (GHz)	I ON/IOFF	SS (mV dec^−1)
9	50	0.5/0.5	200	2.6 × 10^5	72.53
10	50	0.5/0.5	290	10^6	77.76
16	30	−1.1/-2.6	280	1870	117
17	50	0.5/0.5	230	9.3 × 10^4	74.5
20	50	1.0/2.0	—	3.19 × 10^6	125
WSDE^32	20	0.6/1.4	—	5.6 × 10^8	96
This work	14	0.5/0.5	510	1 × 10 ^4	93

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4.4. Circuit level implementation

The circuit-level analysis of the devices involved designing inverters and examining the transient response of inverters based on the GDE-SBMOSFET and conventional SB-MOSFET, as illustrated in Fig. 12. The findings indicated that the inverter circuit utilizing the GDE-SBMOSFET exhibits shorter OFF and ON delays compared to the one employing the conventional SBMOSFET. The calculated percentage decrease in the ON delay is 98%, indicating that the SB-MOSFET-based inverter has a lower delay. Similarly, the OFF delay of the inverter using GDE-SBMOSFET is reduced, with a percentage decrease of 50%. This reduction in both the ON and OFF delays results in the circuit designed with GDESB-MOSFET being faster, effectively reducing the average delay of the circuit.

Fig. 12 (a) SB-MOSFET-based inverter circuit. (b) Transient analysis of the proposed and conventional SB-MOSFET.

5. Conclusion

A novel Schottky Barrier MOSFET structure with an engineered drain and gate has been presented in this study. The proposed device outperforms the conventional devices in terms of various performance measurement parameters, such as the ON current and ON/OFF current ratio, which were increased 26- and 10-fold in comparison to the conventional SBMOSFETs. Additionally, considerable improvements in the SS of 28% and 4% have been achieved by the proposed GDE-SBMOSFET in to the comparison to DSL and conventional SB-MOSFET, respectively. The cut-off frequency (f_T) in the GDE-SBMOSFET (∼510 GHz) has increased 51 and 2 times as compared to that of the conventional SB-MOSFETs. The TG modulates the barrier width of the source and channel interface and controls the ON-state performance measurement parameters, whereas the optimized value of the drain metal workfunction controls the OFF-state performance and SCEs. It has been observed that proposed device is less prone to SCEs and possesses no ambipolar behavior.

Data availability

Information regarding the data may be available upon request, subject to confidentiality agreements.

Conflicts of interest

There are no conflicts to declare.

Acknowledgements

This work was funded and supported by King Faisal University, Eastern Region, Al-Ahsa, Saudi Arabia under grant number KFU242271. We would like to express our sincere gratitude to the funding organization that supported this research project. Their financial support was instrumental in the successful completion of this study.

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