Effects of high-k gate dielectrics on the electrical performance and reliability of an amorphous indium–tin–zinc–oxide thin film transistor (a-ITZO TFT): an analytical survey

Abstract

This study is a numerical simulation obtained by using Silvaco Atlas software to investigate the effect of different types of dielectric layers, inserted between the channel and the gate, on the performance and reliability of an a-ITZO TFT. Replacing the SiO₂ oxide layer with a high-k dielectric layer gives the concept of the electrical thickness, known by the equivalent oxide thickness (EOT) in which the physical thickness (PT) can be increased to improve the device reliability without increasing the effective thickness of the gate dielectric. A range of different high-k dielectric materials was suggested. For low-k SiO₂ (k = 3.9), the electrical parameters extracted are: C_i = 3.45 × 10⁻⁸ F cm⁻², I_on = 2.23 × 10⁻⁶ A, I_off = 2.17 × 10⁻¹³ A, I_on/I_off = 1.02 × 10⁷, EOT = 100 nm, V_T = −0.61 V, μ_FE = 29.75 cm² V⁻¹ s⁻¹, SS = 7.91 × 10⁻² V per decade and V_on = −0.95 V. Replacing SiO₂ by a high-k dielectric material, such as SrTiO₃ (k = 300), leads to effects similar to the effects of reducing the physical thickness of the gate dielectric but without actually reducing this physical thickness. This allows improving the outputs of the a-ITZO TFT as it leads to an increase in C_i, I_on and I_on/I_off to the values C_i = 2.66 × 10⁻⁶ F cm⁻², I_on = 2.86 × 10⁻⁴ A, and I_on/I_off = 8.80 × 10⁹, respectively, and the decrease in EOT, I_off, V_T, μ_FE, SS and V_on to the values EOT = 1.3 nm, I_off = 3.25 × 10⁻¹⁴ A, V_T = −0.428 V, μ_FE = 26.66 cm² V⁻¹ s⁻¹, SS = 6.12 × 10⁻² V per decade and V_on = −0.75 V, respectively, without leakage effects.