Suppression of short channel effects in ferroelectric Si junctionless transistors with a sub-10 nm gate length defined by helium ion beam lithography

Abstract

The performance enhancements of Si junctionless transistors (JLTs) with a short gate length (L_G) below 10 nm by a pronounced ferroelectric (FE) gate dielectric were demonstrated for the first time. A TiN gate with L_G = ∼8 nm was defined by helium ion beam lithography (HIBL) using hydrogen silsesquioxane as a resist. As compared with the paraelectric HfO₂ gate oxide, the FE Hf_0.5Zr_0.5O₂ gate dielectric leads to a suppression of the off-state current (I_OFF) by ∼2 orders of magnitude and a reduction of the minimum subthreshold swing (SS) to ^∼33 mV dec⁻¹, along with an enhancement of the on/off ratio in the reverse-sweep direction in JLTs with L_G = ∼8 nm. JLTs with a long L_G = 5 μm were also investigated for comparison, revealing a decrease of I_OFF by ∼25× and the sub-60 mV dec⁻¹ SS across ∼3 orders of drain current (I_D) under a large drain voltage (V_D = 0.5 V) operation during the reverse sweep in FE JLTs. A time domain analysis indicated that the transient negative capacitance (TNC) effect takes place in the FE gate dielectric. A physical model was proposed to account for the TNC effect and the sub-60 mV dec⁻¹ SS based on the capacitance increase during the FE polarization switching. This study also demonstrates for the first time the fabrication of nanoelectronic devices with a sub-10 nm critical dimension by using the HIBL technique with a damage-free dose.