Performance improvement in monolayered SnS2 double-gate field-effect transistors via point defect engineering

Abstract

Owing to the relatively high carrier mobility and on/off current ratio, monolayered SnS₂ has the advantage of suppressing drain-to-source tunneling for short channels, rendering it a promising candidate in field-effect transistor (FET) applications. To extend the scaling limit of the channel length, we propose to rationally modulate the electronic properties of monolayered SnS₂ through the customized design of point defects and simulate its performance limit in sub-5 nm double-gate FETs (DGFETs), using density functional theory combined with nonequilibrium Green's function formalism. Among all types of point defects, the Se atom as a substitutional dopant (Se_S) can nondegenerately inject electrons into each monolayered (ML) SnS₂ 2 × 4 × 1 supercell, whereas the Sn vacancy (V_Sn) defect exhibits an opposite doping effect. By adjusting the lateral Schottky barrier height between electrodes and the channel region, the on-state current (I_on), on/off ratio, delay time, and power-delay product in the formed n-type Se_S-doped SnS₂ and p-type V_Sn-doped SnS₂ DGFETs with a channel length of 4.5 nm have been remarkably improved, fulfilling the requirements of the International Technology Roadmap for Semiconductors (ITRS) for high-performance applications in the 2028 horizon. Our work unveils the great significance of point defect engineering for applications in ultimately scaled electronics.