Issue 42, 2023

Sub-9 nm high-performance and low-power transistors based on an in-plane NbSe2/MoSe2/NbSe2 heterojunction

Abstract

Due to the ability to reduce the gate length of field-effect transistors (FETs) down to sub-10 nm without obviously affecting the performance of the device, the utilization of two-dimensional (2D) semiconductor materials as channel materials for FETs is of great interest. However, in-plane 2D/2D heterojunction FETs have received less attention in previous studies than vertical van der Waals heterojunction devices. Based on the above reasons, this study has investigated the transport properties of an in-plane NbSe2/MoSe2/NbSe2 heterojunction FET with different gate lengths by using ab initio quantum transport simulation. The results reveal that a gate length of sub-9 nm gives the device a low subthreshold swing down to 62 mV dec−1 and a high on-state current up to 1040 μA μm−1. Most importantly, the on-state current, delay time, and power dissipation of the FET with the optimized channel length can nearly meet or even exceed the high-performance and low-power requirements of the International Technology Roadmap for Semiconductors. The findings for this FET can provide the design and development guidance for other in-plane heterojunction electrical devices in the post-Moore era.

Graphical abstract: Sub-9 nm high-performance and low-power transistors based on an in-plane NbSe2/MoSe2/NbSe2 heterojunction

Supplementary files

Article information

Article type
Paper
Submitted
07 Sep 2023
Accepted
25 Sep 2023
First published
28 Sep 2023

Nanoscale, 2023,15, 17029-17035

Sub-9 nm high-performance and low-power transistors based on an in-plane NbSe2/MoSe2/NbSe2 heterojunction

Z. Cao, X. Guo, K. Yao and L. Zhu, Nanoscale, 2023, 15, 17029 DOI: 10.1039/D3NR04514E

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