Enhancing the crystallinity and dielectric performance of ALD-grown SrTiO3 films by introducing a sub-nm-thick Pt layer

Abstract

SrTiO₃ (STO), which has an exceptionally high dielectric constant, is a promising candidate for capacitor dielectrics for dynamic random-access memory (DRAM) applications. However, during atomic layer deposition (ALD), unwanted interfacial reactions with substrates, such as Ru, hinder its integration, which results in compositional nonuniformity and poor crystallinity. In this study, an ultrathin Pt layer (≤ 1 nm) is introduced as a reaction barrier, which effectively suppresses these interfacial reactions. This approach enabled the growth of high-quality stoichiometric STO films with enhanced crystallinity and dielectric performance. Despite its sub-nanometer thickness, the Pt layer notably improved the compositional uniformity and promoted film crystallization, which significantly increased the dielectric constants and reduced the equivalent oxide thickness (EOT). Post-deposition annealing (PDA) at 500 °C, compatible with DRAM fabrication, yielded an EOT of 0.34 nm with stable leakage currents and long-term reliability for STO films thinner than 10 nm. Furthermore, the area-selective growth characteristic of the ultrathin Pt layer eliminated the critical etching challenges of Pt, which facilitated selective growth on Ru and avoided unwanted growth on dielectric materials such as SiO₂. This study presents a scalable, low-temperature solution for integrating STO into DRAM capacitors, thereby addressing critical fabrication challenges and advancing the potential of STO in memory applications.