Dual-port ferroelectric NAND flash memory for large memory window, QLC programmable and disturbance-free operations

Abstract

The ferroelectric NAND flash memory devices have garnered interest because of their rapid switching speed, low operating voltage, and superior reliability in comparison to conventional charge-trap flash memory. In particular, hafnia-based ferroelectrics have been intensively studied thanks to their relatively low crystallization temperature, CMOS compatibility, and excellent scaling characteristics. However, when processing the 3D integration, FeNAND devices based on hafnia encounter thermal instability issues due to the high process temperature required for both deposition and annealing of the poly-Si channel. Furthermore, FeNAND devices suffer from the read/pass disturbance and narrow memory window (MW) stems from the sub-loop characteristics and intrinsic small coercive field of hafnia ferroelectrics. To address these issues, we propose oxide channel dual-port FeNAND devices with additional gate dielectric and gate metal on the opposite side of the ferroelectrics from the channel layer. The thermal stability and disturbance issues are resolved with the low-temperature process oxide channel (<300 °C) and an extra gate stack. We experimentally verified that our devices show a broad MW range of 10 V, operate using quad-level-cell technology, and exhibit excellent levels of reliability. In addition, considering the findings from the experiments, we propose a 3D process integration strategy and evaluate the characteristics of dual-port 3D FeNAND devices using TCAD modeling.

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Introduction

Over the past decade, charge trap NAND flash memory (CTF-NAND) devices, employing electron tunneling and capturing mechanisms, have been widely utilized across various electronic devices owing to their substantial storage capacity based on low-cost fabrication.^1,2 In particular, vertically stacked NAND (V-NAND) flash memory devices provide high-density memory solutions.^3–5 Due to the nature of CTF-NAND, which requires sufficient energy band bending in the tunneling oxide for programming (PGM) and erasing (ERS) operations, the operational voltage (20 V) and the time (10⁻³ s) increase.¹ Furthermore, there exists a clear limitation in CTF-NAND, whereby the early degradation of the tunneling oxide during the electron and hole tunneling processes leads to a deterioration in endurance characteristics (10⁴ cycles).³ Currently, there is ongoing research on hafnia-based ferroelectric NAND flash memory (FeNAND) devices that utilize polarization switching to overcome the limitations of conventional CTF-NAND.^6–10 Recent research has shown that FeNAND devices have exceptional qualities, including high speed, low-voltage operation, and outstanding reliability suitable for use in high-density NAND flash memory devices.

Nevertheless, hafnia ferroelectrics are still challenging to integrate into NAND flash memory owing to their intrinsic limitations, such as thermal instability,^11–13 relatively low coercive electric field (E_C),^14,15 and sub-loop characteristics.^16,17 Considering the fabrication process of FeNAND devices, the high temperature poly-Si channel process is followed by the deposition of the ferroelectric layer in accordance with the conventional V-NAND fabrication sequence.¹⁸ However, this process can seriously deteriorate hafnia ferroelectrics. Moreover, the sub-loop features of hafnia ferroelectrics allow for polarization switching to occur even under low-voltage settings, making it difficult to achieve disturbance-free multi-level-cell (MLC) operation in FeNAND devices, especially when the memory window (MW) is quite small, below 4 V. Hence, it is necessary to devise techniques for FeNAND MLC operation that employ channel materials capable of being deposited and activated at low temperatures, while also extending the effective MW and minimizing disturbances with the stored state in each cell.

Prior research on FeNAND devices mostly concentrated on the MF(I)S or MFMIS structures, where M represents metal, F represents ferroelectric, I represents insulator, and S represents semiconductor.^19–23 A significant amount of research has been carried out on FeNAND device structures with MF(I)S configurations, with the goal of achieving seamless compatibility with V-NAND integration methods. Nevertheless, FeNAND devices with MF(I)S structure still have difficulties associated with limited MW, interference, and reliability concerns. The structure of MFMIS can guarantee a high MW by ensuring a capacitance ratio match between the ferroelectric and dielectric insulator layers. However, the integration of thick gate stacks and metal interlayers into 3D architectures is complicated, and problems related to disturbance continue to exist. Therefore, the importance of 3D stacking FeNAND devices with uninterrupted operation has also been increased.

Our proposal involves the use of dual-port FeNAND devices with oxide channels, which consist of heterogeneous gate insulators made of both ferroelectric and dielectric materials. Fig. 1a shows the schematic of the device, whereas Fig. 1b shows the transmission electron microscope (TEM) image. In order to decrease the elevated thermal budget of the poly-Si fabrication process, the channel layer was made of Al-doped InZnSnO (Al:IZTO). The Al:IZTO oxide semiconductor demonstrates superior properties when subjected to low-temperature procedures of 300 °C or below. This effectively resolves the issue of thermal degradation in the underlying ferroelectric layer caused by the poly-Si fabrication technique.^20,24,25 Additionally, to address potential mobility issues in the oxide channel, we utilized Al:IZTO, which is known for its relatively high mobility.²⁶ Compared to the widely used IGZO, Al:IZTO exhibits improved carrier conduction paths and enhanced mobility due to the expanded overlap of the symmetric spherical 5s orbitals of In and Sn ions. Furthermore, Al:IZTO can be manufactured using processes and equipment similar to those employed for IGZO films. Therefore, Al:IZTO is regarded as an enhanced oxide semiconductor of IGZO, which is why we selected it as our channel layer. To form a dual-port layout, the dielectric gate insulator and an extra gate metal are placed on the opposite side of the ferroelectrics compared to the channel layer, which allows for a wide MW. Fig. 1c illustrates the mechanism of MW amplification in a dual-port FeNAND device configuration. It is important to understand that the position of the channel can be altered by adjusting the bias of the writing gate (WG, ferroelectric side gate) and read gate (RG, dielectric side gate). Applying voltage to the WG causes electrons to accumulate in proximity to the ferroelectric gate insulator, resulting in the formation of the channel. In contrast, the application of voltage to the RG causes electrons to accumulate in proximity to the dielectric gate insulator. Nevertheless, the ferroelectric maintains a constant remanent polarization (P_r) throughout. Consequently, the application of voltage to the WG and RG alters the effective capacitance, resulting in the expansion of the MW according to the capacitance equation depicted in Fig. 1c. The MW with RG read operation (MW_RG) is a capacitance matching parameter with RG read (γ_RG) times wider than the MW with WG read operation (MW_WG). The γ_RG is denoted as C_WG/C_DE or ∂V_th,WG/∂V_th,RG. C_WG represents the equivalent capacitance of the series connection of the ferroelectric and channel layers, while C_DE represents the capacitance of the dielectric layer. V_th,WG refers to the threshold voltage with WG read, and V_th,RG refers to the threshold voltage with RG read.²⁷ In addition, we successfully accomplished disturb-free operation using the dual-port configuration. When performing read and pass operations, the electric field (E-field) across the ferroelectric layer is decreased and disturbance is minimized by using RG. Finally, this work presents a technique for integrating dual-port FeNAND devices in a 3D structure. It also includes TCAD simulation results that estimate the electrical characteristics of the integrated devices to evaluate the viability of this 3D integration.

Fig. 1 (a) Schematics, (b) TEM image, and (c) operation principle of a dual-port ferroelectric NAND (FeNAND) device. Thanks to the heterogeneous gate dielectrics (ferroelectric HZO and dielectric Al₂O₃) used as bottom and top gate dielectrics, the dual-port FeNAND devices expand their memory window (MW).

Result and discussion

The energy band diagrams of poly-Si channel and oxide semiconductor channel in dual-port FeNAND gate stacks are depicted in Fig. 2a(i) and (ii), respectively, to illustrate their differences. Typically, the channel in conventional poly-Si FeNAND devices can easily set to three distinct states (accumulation, depletion, and inversion states) owing to its narrow bandgap. Therefore, during the switching operation, electron and hole carriers interact with dipoles of the ferroelectric. On the other hand, the oxide channel remains in the depletion state during ERS operation due to its wide energy-bandgap, making the polarization switching of ferroelectrics challenging.²⁸ To address this issue, we employ the dual-port structure along with the PGM (as shown in Fig. 2a(iii)) and ERS (as shown in Fig. 2a(iv)) operating schemes, utilizing the RG-assisted double gate (DG) switching mechanism. Fig. 2b provides a visual representation of the specific schemes used for the DG switching approach. During ERS operation, the RG in the DG switching approach facilitates the transfer of the channel from a depletion state to an accumulation state, which then enables the polarization to switch further. In other words, a portion of the channel transforms into an accumulation state and provides carriers that can interact with dipoles when the ferroelectric material switches. Hence, the MW of dual-port FeNAND devices with V_WG read is capable of being widened by DG switching approach. The ferroelectricity of crystallized HZO was characterized using P–E curve and XRD measurements as shown in Fig. S1a and b (ESI†). The I_D–V_WG curves of FeNAND devices illustrate the impact of the DG switching approach, as shown in Fig. 2c. The DG switching approach enhances the switching characteristics, resulting in a 75% extension of the MW (from 0.4 V to 0.7 V) compared to the single gate (SG) switching approach. Fig. 2d demonstrates the relationship between MW and V_RG. As V_RG bias increases, the MW extends and then saturates after the dipole is fully switched over applying 30 V of V_RG. The reason for MW saturation at excessive V_RG bias is that the dielectric gate insulator has a relatively low dielectric constant (∼9, Al₂O₃) and thick thickness (∼55 nm). This issue can be resolved through scaling of the dielectric gate insulator.

Fig. 2 (a) The energy band diagrams of two different dual-port FeNAND devices: (i) devices with a poly-Si channel and (ii) devices with an oxide semiconductor channel. The dual-port structure and following (iii) PGM and (iv) ERS schemes based on RG assist the channel transition from depletion to the accumulation state, then leads to the further switching of the polarization. (b) Operation schemes of double gate (DG) switching method. (c) I_D–V_WG curves with single gate switching (red) and DG switching (blue) methods. (d) The memory window as a function of V_RG with the DG switching approach.

To confirm the V_th shift by the back gate bias applied on the opposite side of the gate during the read operation, the I_D–V_G curves of the dual-port FeNAND devices were analyzed. The curves for WG bias and RG bias are shown in Fig. 3a and b, respectively. The full-range I_D–V_G curves of dual-port FeNAND devices are depicted in Fig. S2a and b (ESI†). The V_th was adjusted by the WG and RG bias in response to the back gate bias. The shift in V_th is dependent on γ, which is directly proportional to the capacitance of the gate insulators. The capacitance matching parameter with WG read (γ_WG) and RG read were obtained by analyzing the slope of V_th,WGversus V_RG and V_th,RGversus V_WG curves. Fig. 3c and d illustrate the relationship between V_th and WG with regard to V_RG, and the relationship between V_th and RG with respect to V_WG, respectively. The extracted γ_WG and γ_RG values are 0.11 and 15.1, respectively. The capacitance of the Hf_0.5Zr_0.5O (HZO) gate insulator on the WG side is greater than the capacitance of the Al₂O₃ gate insulator on the RG side. As a result, the change in V_th is significantly greater when V_WG is utilized as a back gate bias. The γ_RG values also suggest that the MW can be enhanced by a factor of up to 15.

Fig. 3 The variation in threshold voltage (V_th) of dual-port FeNAND devices with different WG and RG bias. (a) The I_D–V_G curves with RG bias and WG read, and (b) the I_D–V_G curves with WG bias and RG read. The V_th is shifted due to the channel conductance change by RG and WG bias. (c) V_thversus applied bias with WG read and (d) RG read. The capacitance matching parameters (γ_WG & γ_RG) are extracted from the slope between V_th and bias.

The I_D–V_G curves with RG read are measured, as shown in Fig. 4a, to verify the impact of memory window enhancement in dual-port FeNAND devices. The size of the MW is increased from 0.7 V to 10 V through the utilization of the capacitance matching effect. The relationship between the MW_th,WG and MW_th,RG and the write amplitude is depicted in Fig. 4b. A 1 μs write pulse is applied to the WG, and a read operation is performed using both the WG and RG. As previously shown, MW_RG has a larger MW compared to MW_WG. Fig. 4c depicts the correlation between MW_th,RG as well as MW_th,WG. We computed the value of γ_RG by utilizing the gradient of MW_RG and MW_WG. Consequently, MW_RG was determined to be 12.2 times more than MW_WG. The obtained γ_RG value is 12.2, which has a lower slope compared to the calculated value of 15.1. The slope of the calculated value is determined by V_th,RG, and V_WG, whereas the slope of the obtained value is determined by MW_RG and MW_WG. This situation arises from the fact that each measurement method employs a distinct operational scheme. Fig. 3a employed a DC scheme bias to evaluate the I_D–V_G while applying a back gate bias. In Fig. 4a, a pulse scheme bias was used to compare MW. Thus, it is hypothesized that distinct γ_RGs were obtained by the use of DC and pulse methods. However, it demonstrates that dual-port FeNAND devices have significantly increased memory write capability in all operational scenarios.

Fig. 4 MW enhancement of dual-port FeNAND devices with RG. (a) The I_D–V_G curves with RG. (b) MW vs. write pulse amplitude. Due to the cap. matching effect, the MW_RG is enhanced until 10 V. (c) MW_RGvs. MW_WG curves. The capacitance matching parameters (γ_RG) is extracted.

Fig. 5a and b display the endurance and retention characteristics of dual-port FeNAND devices with RG read. We applied the pulse with a pulse amplitude of 8 V and a pulse width of 1 μs at WG, and read the MW with RG. While the MW_RG experiences an increase in voltage from 0.7 V to 10 V, the expansion of the MW only works during read operations. Thus, the dual-port FeNAND devices have exceptional reliability features for more than 10⁸ cycles and up to 10⁵ seconds. Fig. 5c shows disturbance behaviors of single-port FeNAND devices with pulse bias amplitude. When the pulse bias amplitude and the number of cycles increase, the V_th,WG change (ΔV_th,WG) is changed up to 34%. The detailed disturbance characteristics as a function of pulse amplitude and pulse width are shown in Fig. S3a–c (ESI†).

Fig. 5 (a) Endurance and (b) retention properties of dual-port FeNAND devices with RG read. Disturbance behaviors of (c) single-port and (d) dual-port FeNAND devices as a function of pulse bias amplitude. (e) The verification of QLC for dual-port FeNAND devices.

Single-port FeNAND devices experience a disturbance issue due to the write and read operations performed on the same gate. On the other hand, the issue can be resolved by physically dividing the gate into WG and RG in dual-port FeNAND devices. Fig. 5d illustrates the disturbance behaviors of dual-port FeNAND devices, using different pulse amplitudes. The V_th,RG change (ΔV_th,RG) exhibits an insignificant magnitude of less than 6%. The experimental results demonstrate that the dual-port FeNAND successfully addresses the disturbance issue. Fig. 5e depicts the functioning of dual-port FeNAND devices for QLC operation. To characterize QLC operations of dual-port FeNAND, the incremental step pulse programming (ISPP) method was utilized. We applied a bias by increasing the pulse amplitude from 5 V in 0.2 V steps. The pulse width was set to 1 μs. The detailed ISPP method and V_th transitions are shown in Fig. S4a–c (ESI†). The enhanced MW allows for the 16 states without overlapping. The spacing between each state is also ensured to have about 0.2 V spacing regardless of the dispersion.

We used the simulation framework in Fig. S5a (ESI†) to evaluate the performance of the 3D vertical FeNAND devices based on the electrical properties of a 2D planar structure. The conventional ferroelectric model, with its challenges in precisely executing the read operation based on the ferroelectric state with remnant polarization (P_FE), struggles to accurately represent the sub-loop operation. Hence, we referenced the approach in (ref. 29) to convert and substitute the degree of ferroelectric polarization switching at the interface between the ferroelectric and the IZTO channel into an equivalent fixed charge (Q_fix = P_FE/1.6 × 10¹⁹), as depicted in Fig. S5b (ESI†). Further validating our methodology, Fig. S5c and d (ESI†) compare the I_D–V_G characteristics based on WG and RG read operation with the simulation results, demonstrating a match between the two. This comparison clearly substantiates the effectiveness of our approach.

Using the simulation framework indicated before, it is possible to integrate the prior gate stack into dual-port 3D FeNAND devices by testing the PGM, ERS, and read operations. As shown in the circuit design of Fig. 6a, the system consists of four strings, each consisting of five cells, as seen in Fig. 6b. We set the cell pitch size and the oxide spacers between cells to 50 nm, using SiO₂ as the dielectric for the oxide spacers. The gate stack configuration was kept the same as that of the prior 2D planar device structure. Next, we conducted a thorough examination of the accuracy and reliability of the PGM, ERS, and read operations within the 3D multi-string structure depicted in Fig. 6c. Fig. 6d illustrates the magnitude of the electric field that is exerted on the FE layer in each string during the PGM/ERS operations, following the X-cut direction as shown in Fig. 6b. During the PGM operation, a strong electric field is selectively applied to the specific string and cell, whereas the electric field intensity in other cells is insignificant. It is crucial for reliable cell operation in a 3D NAND system, where different cells share word lines (WL) or bit lines (BL), to have disturb-free operation. This is because the intrinsic polarization switching mechanism of ferroelectrics can lead to accumulative switching or unwanted polarization state variation even under sub-coercive field intensity. In the ERS operation, it is verified that the electric field is efficiently applied to all target cells, with the opposite polarity compared to the PGM operation.

Fig. 6 (a) 4 strings circuit diagram, (b) 3D scheme, and TCAD simulation structure of 3D dual-port FeNAND devices. (c) Operation schemes of 3D dual-port FeNAND devices. (d) Polarization profile during the PGM and block ERS operation of strings 1,2,3, and 4. The number of cell was set to five, and polarization profile was extracted following the X-cut line as notified in (b).

Following the PGM/ERS operations, we verified the read operation through WG and RG. Fig. 7a shows that the I_D–V_G characteristics vary with the read operation. We observe a significantly enlarged effective MW due to the body effect when we use the RG read method instead of the WG, mirroring the findings from the previous 2D planar cells. Fig. 7b demonstrates the advantage of RG read operation from the perspective of disturbance issues. Since the WG read directly applies the pass and read voltage to the gate adjacent to the FE cell, it applies a relatively high electric field to the FE layer, resulting in unavoidable disturbance issues. Our simulation results indicate that when the read voltage exceeds 5.4 V, the ferroelectric's electric field surpasses the E_c value, leading to a reversal in the polarization switching direction, meaning the failure of the memory operation. In contrast, the read voltage is applied from the RG located opposite the FE layer for the RG read operation. Even if the read voltage increases substantially, virtually no electric field is applied to the FE layer. Therefore, reliable functioning is achievable through negligible disturbance, even with repeated read operations. Fig. 7c shows the electric field profile when a pass voltage of 10 V and a read voltage of 10 V are applied. It can be seen that a strong electric field is applied to the FE layer for WG read, while for RG read, it is applied to Al₂O₃ layer adjacent to the RG. This confirms that using RG read can resolve disturbance issues while significantly securing a larger MW.

Fig. 7 (a) I_D–V_G curves of the selected cell after the program and erase in 3D NAND string. (b) The effective electric field curves and (c) 3D schematics applied to the ferroelectric during WG and RG read operation.

Subsequently, we conducted experiments to determine the most efficient RG configuration for the read operation of 3D dual-port FeNAND devices. Fig. 8a and b depict the string structures, showing the RG splitting and dividing for each cell in Fig. 8a and remaining undivided with a single RG for all cells in Fig. 8b. As depicted in Fig. 8c, the memory window, as determined by MW's governing equation, exhibits an inverse relationship with the C_DE. The effective area (A_DE,U) of the DE layer in contact with the RG and its capacitance value (C_DE,U) are significantly greater when an undivided RG is utilized as opposed to a divided RG. This increase reduces the amplification impact of the memory window caused by the body effect. Fig. 8d illustrates the correlation between the number of cells and the variations in the MW during the RG read process. With an increase in the number of cells, the C_DE,U values also increase in the undivided RG structure, leading to a notable reduction in MW. Therefore, when employing the RG operation, it is essential to isolate the read gate for every individual cell, which requires a particular process scheme. Fig. S6 (ESI†) illustrates the procedural arrangement for the divided RG structure. It should be noted that our simulation did not consider several performance variables that may arise in a real 3D dual-port FeNAND architecture. In actual cases, the reduction in the effective area of the FE layer may result in conductivity variations due to the random configuration of FE/DE in the polycrystalline structure and potential uniformity issues during ferroelectric material deposition in high aspect ratio conditions.

Fig. 8 (a) Dual-port 3D FeNAND device structures with divided and (b) undivided RG. (c) Governing equation of MW for divided and undivided RG structures. (d) The variation of MW with gate structures and the number of cells.

Conclusion

In summary, we performed an experimental demonstration of dual-port FeNAND devices with oxide channels for low process temperatures, a wide MW, and disturbance-free operations. By utilizing an oxide channel, we were able to avoid the crystallization process of the poly-Si channel required to secure the mobility, thereby preventing subsequent thermal damage to the FE layer. The devices show a high MW value of 10 V, QLC operations, and remarkable endurance over 10⁸ cycles by our unique DG switching approach and dual-port configuration to prevent the reduction in polarization switching caused by the intrinsic n-type nature and insufficient screening hole charge of the oxide channel. Each of those numbers exceeds the performance of conventional NAND flash and FeNAND memory devices. In addition, we introduced a 3D integration strategy for dual-port FeNAND based on the conventional 3D NAND integration scheme, sharing the same deposition sequence of layers as our experimental demonstration. Then, we have also verified the operation of dual-port 3D FeNAND devices through the experimentally calibrated TCAD model. We verified that the read operation utilizing RG significantly decreases the field applied to the FE layer, in contrast to the WG-based read operation. This results in minimal disturbance to the stored polarization state in the FE layer, even with repeated read operations. We also suggested that the RG should be divided for the realization of dual-port operation with the increasing stacks of 3D dual-port FeNAND.

Experimental method

We fabricated the dual-port FeNAND device on a Si/SiO₂ wafer. We sputtered 100 nm-thick TiN as the wafer gauge. Next, we deposited 20 nm-thick HZO as the ferroelectric gate insulator using plasma-enhanced-atomic-layer-deposition (PEALD). We put a protective layer of 50 nm TiN on top of the HZO to crystallize it, and then we heated it quickly at 600 °C for 10 seconds in an N₂ environment. Next, we used the SC1 (NH₄OH:H₂O₂:H₂O) etchant to remove the sacrificial layer. We sputtered 10 nm-thick Al:IZTO for the channel layer. We used 100 nm-thick Mo as the source and drain electrodes. PEALD deposited 55-nm-thick Al₂O₃ as the dielectric gate insulator. Finally, PEALD sputtered 100 nm-thick TiN as the gate insulator. The dual-gate switching approach uses the RG as a switching-assisted gate.

We evaluated the electrical characteristics, such as I_D–V_G curves, memory window, and reliability (endurance and retention), of FeNAND devices using the Keithley 4200A. We used the JEM-2100F HR by JEOL to capture the TEM image of a dual-port FeNAND device. Sentaurus TCAD carried out the 3D FeNAND device simulations.

Abbreviations

CTF-NAND	Charge trap NAND flash memory
V-NAND	Vertically stacked NAND
PGM	Programming
ERS	Erasing
FeNAND	Ferroelectric NAND flash memory
E C	Coercive electric field
MLC	Multi-level-cell
MW	Memory window
MFMIS	M: metal, F: ferroelectric, I: insulator, S: semiconductor
TEM	Transmission electron microscope
Al:IZTO	Al-doped InZnSnO
WG	Write gate
RG	Read gate
P r	Remanent polarization
MWRG	MW with RG read operation
γ RG	Capacitance matching parameter with RG read
MWWG	MW with WG read operation
C WG	Equivalent capacitance of series connection of ferroelectric and channel layers
C DE	Capacitance of dielectric layer
V th,WG	Threshold voltage with WG read
V th,RG	Threshold voltage with RG read
E-field	Effective electric field
DG	Double gate
SG	Single gate
γ WG	Capacitance matching parameter with WG read
ΔVth,WG	V th,WG change
ΔVth,RG	V th,RG change
P FE	Ferroelectric state with remnant polarization
WL	Word line
BL	Bit line
A DE,U	Effective area of undivided RG
C DE,U	Dielectric capacitance value of undivided RG
PEALD	Plasma-enhanced-atomic-layer-deposition

Author contributions

The manuscript was written through contributions of all authors. All authors have given approval to the final version of the manuscript.

Data availability

The datasets used in this study are available from the corresponding author on reasonable request.

Conflicts of interest

There are no conflicts to declare.

Acknowledgements

This work was supported by the Technology Innovation Program (RS-2023-00231985, RS-2023-00235655) funded By the Ministry of Trade, Industry & Energy (MOTIE, Korea). This work was also supported by the National Research Foundation of Korea (NRF) grant funded by the Korea government (MSIT) (No. RS-2023-00260527).

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Footnotes

† Electronic supplementary information (ESI) available: Fig. S1: Polarization versus electric-field curve and XRD spectra of ferroelectric HZO layer; Fig. S2: Full-range I_D–V_G curves of dual-port FeNAND devices; Fig. S3: Disturbance behaviors of single-port FeNAND devices; Fig. S4: ISPP method schematics and transition of V_th for dual-port FeNAND devices; Fig. S5: Simulation framework, methodology of fixed charge for polarization switching simulation and verification of consistency between TCAD models and experimental data; Fig. S6: 3D FeNAND devices integration process schematics and comparison of the number of bits per unit cell area between conventional and dual-port FeNAND devices. See DOI: https://doi.org/10.1039/d4tc02210f

‡ H. Joh and S. Lee contributed equally.

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