Issue 8, 2017

The lab-on-PCB approach: tackling the μTAS commercial upscaling bottleneck

Abstract

Commercialization of lab-on-a-chip devices is currently the “holy grail” within the μTAS research community. While a wide variety of highly sophisticated chips which could potentially revolutionize healthcare, biology, chemistry and all related disciplines are increasingly being demonstrated, very few chips are or can be adopted by the market and reach the end-users. The major inhibition factor lies in the lack of an established commercial manufacturing technology. The lab-on-printed circuit board (lab-on-PCB) approach, while suggested many years ago, only recently has re-emerged as a very strong candidate, owing to its inherent upscaling potential: the PCB industry is well established all around the world, with standardized fabrication facilities and processes, but commercially exploited currently only for electronics. Owing to these characteristics, complex μTASs integrating microfluidics, sensors, and electronics on the same PCB platform can easily be upscaled, provided more processes and prototypes adapted to the PCB industry are proposed. In this article, we will be reviewing for the first time the PCB-based prototypes presented in the literature to date, highlighting the upscaling potential of this technology. The authors believe that further evolution of this technology has the potential to become a much sought-after standardized industrial fabrication technology for low-cost μTASs, which could in turn trigger the projected exponential market growth of μTASs, in a fashion analogous to the revolution of Si microchips via the CMOS industry establishment.

Graphical abstract: The lab-on-PCB approach: tackling the μTAS commercial upscaling bottleneck

Article information

Article type
Critical Review
Submitted
06 Febr. 2017
Accepted
03 Marts 2017
First published
06 Marts 2017
This article is Open Access
Creative Commons BY-NC license

Lab Chip, 2017,17, 1388-1405

The lab-on-PCB approach: tackling the μTAS commercial upscaling bottleneck

D. Moschou and A. Tserepi, Lab Chip, 2017, 17, 1388 DOI: 10.1039/C7LC00121E

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