High performance ferroelectric field-effect transistors for large memory-window, high-reliability, high-speed 3D vertical NAND flash memory

Abstract

A ferroelectric field-effect transistor (FeFET) has significant potential as a leading contender to replace current NAND flash memory owing to its high operation speed, low power consumption, and highly attractive nonvolatile characteristics originating from its two stable polarization states. However, the representative gate stack of a metal–ferroelectric–insulator–semiconductor (MFIS) has obvious limitations owing to the large voltage drop across the gate insulator, such as charge injection and trapping, low endurance, and a small memory window. Herein, we introduce unique material and structural approaches to address the crucial problems of previous FeFETs. For the material approach, we engineer the grain size by adjusting the Zr content in the HfZrO film and perform a high-pressure annealing process to maximize the tensile strain on the ferroelectric layer during crystallization. We obtain a large memory window (approximately 5 V) for multi-bit operation (eight states), high program/erase speed (<20 ns), and outstanding endurance (>10⁹ cycles) of FeFETs based on the gate stack of a metal–ferroelectric–metal–insulator–semiconductor (MFMIS). For the structural approach, we present a novel 3D vertical MFMIS ferroelectric NAND flash array, wherein the gate stack is designed to induce active switching of the ferroelectric film even with a vertical structure. Finally, the operation scheme of a 3D ferroelectric NAND flash optimized for multi-string operations free from program disturbance is logically probed using technology computer-aided design simulations with a carefully calibrated model. The 3D ferroelectric NAND flash memory can pave the way for next-generation nonvolatile memory devices based on its superior performance.