Scalable fabrication of a complementary logic inverter based on MoS₂ fin-shaped field effect transistors

Abstract

Integration of high performance n-type and p-type field-effect transistors with complementary device operation in the same kind of layered materials is highly desirable for pursuing low power and flexible next-generation electronics. In this work, we have shown a well-mannered growth of MoS₂ on a fin-shaped oxide structure and integration of both n-type and p-type MoS₂ by using a traditional implantation technique. With the advance of the fin-shaped structure, the maxima and the effective ON current density for the MoS₂ fin-shaped field-effect transistors are respectively obtained to be about 50 μA μm⁻¹ (normalized by the circumference of the fin) and around 500 μA μm⁻¹ (only normalized by the fin size), while its ON/OFF ratio is more than 10⁶ with low OFF current of a few pA. Based on our n-type and p-type MoS₂ fin-shaped field-effect transistors, the complementary MoS₂ inverter with a high DC voltage gain of more than 20 is acquired. Our results provide evidence for complementary 2D material operation in the same materials, a promising avenue for the development of high performance and high-density complementary 2D electronic devices.

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Conceptual insights

In this study, a new concept has been demonstrated, which is the integration of both fin-shaped n-type and p-type MoS₂ field effect transistors by using a traditional implantation technique to show high performance two-dimensional material electronics. Compared to the existing research, this concept is compatible with the Si-based fabrication process and is industrially feasible for the future fabrication of advanced devices. The additional insight to the nanoscience field in this work is to provide a good idea (fin-shaped MoS₂ FETs) for enhancing the effective current density to act as a promising protocol of new future CMOS applications.

Moore's law states that the number of transistors in the same chip area doubles approximately every two years.¹ This long-persisting law, however, is challenged by the existence of leakage current due to the short channel effect. In order to eliminate the short channel effect, scientists have executed several device constructions.^2–4 A fin-shaped field effect transistor (fin-FET), one of the most popular designs, conducts fin-like channels forming a wrap-around gate structure and provides superior electrical control compared to planar structures.⁵ As a consequence, the leakage current can then be suppressed while the device performance is still augmented. Other methods such as applying new materials instead of silicon while scaling down the channel length of FETs are worthy of consideration. Two-dimensional (2D) layered materials such as transition metal dichalcogenides (TMDs) have received huge attention soon after the discovery of graphene.⁶ Physical properties such as electrical transport properties and flexibility endow TMDs with potential applications in electronic, spintronic and optical devices.^7–12 TMDs as channel materials in future FET applications are one promising choice; among these materials, MoS₂ is regarded as one of the candidates due to its atomically thin and flat nature as well as high mobility and large band gap.^13–17 MoS₂ itself, however, seems not suitable for acting as a complementary metal-oxide semiconductor (CMOS) since it generally shows only n-type behavior. Most reported CMOS configuration-based 2D layered materials use both MoS₂ and WSe₂ as n-type and p-type semiconductors, respectively.^18,19 However, growing two materials in the same chip/wafer is too complicated for mass production, since it is hard to combine it with the current semiconductor fabrication process. The ideal case is similar to silicon and germanium, fabricating n-type and p-type channels on the same semiconductor material. Some people have reported that the change from n-type to p-type channel can be induced by ion implantation.²⁰ Another way is to utilize a high work function material as a buffer layer contacting with the MoS₂ film, leading to hole carriers dominating the MoS₂ transport behavior. For example, Ali's group has succeeded in demonstrating a p-type MoS₂ transistor with a MoO_x/MoS₂ contact.²¹

Since buffer layering is not a standard process and it may degrade the performance of devices during procedures, it is highly desirable to figure out the whole silicon compatibility in the fabrication process. There is a previous simulation study showing that MoS₂ contacting with high work function silicon may bring about hole-dominated carrier injection in MoS₂ FETs.²² Based on the implication of this study, we have meticulously fabricated devices and successfully demonstrated both n-type and p-type FETs made of MoS₂ film in an identical chip by directly growing MoS₂ on different types of source/drain silicon electrodes. Furthermore, in order to take advantage of its high current density, the MoS₂ film is intentionally grown on the fin oxide structure. The chemical vapor deposition (CVD) of MoS₂ can fully cover the fin oxide structure which is compatible with the Si-based fabrication process and is industrially feasible for the future fabrication of advanced devices. We have also shown that the complementary MoS₂ (CMOS2) inverter has a dc voltage gain of more than 20. This CMOS2 is based on n-type and p-type MoS₂ and is promising for acting as the protocol of new future CMOS applications.

The device fabrication in this work is extended from our previously reported study on the advanced 10 nm channel-length MoS₂ devices.²³ The main difference from our previous study, in terms of device geometry, is the fin-shaped structure for the channel. The whole process flow is completely described in Fig. S1 (ESI†). The typical MoS₂ thin film islands and their Raman spectrum (A_1g − E_2g = 19 cm⁻¹) are shown in Fig. S2 (ESI†), which indicates the presence of the crystal MoS₂ film near the S/D electrodes. A schematic plot of the CVD system and the thermal cycle used for layered MoS₂ deposition are shown in Fig. S3 (ESI†).²⁴

Fig. 1(a) shows a schematic plot of a MoS₂ fin-shaped field effect transistor (a MoS₂ fin-FET), which displays an original idea that the SiO₂ fin structure is fully covered with a continuous layered MoS₂ film as a fin-shaped conduction channel. The top-view SEM image of one of the MoS₂ fin-FETs is shown in Fig. 1(b), where the gate electrode crosses over between the source (S) and drain (D) with the surface contact area of about 300 nm² and the distance between S and D is 100 nm. The cross-section TEM image shown in Fig. 1(c) clearly displays the fully oxidized SiO₂ fin structure with layered MoS₂ coverage with a high-k metal gate stack. Note that there is a thin SiO₂ layer (∼3 nm) that we intentionally grow on top of the continuous 3 nm (5 layers) MoS₂ film as the buffer layer for high quality HfO₂ deposition, as shown in Fig. 1(d). Without this buffer layer, it is easy to damage the MoS₂ film when an ALD process is conducted. In addition, the uniformity of the film still needs to be improved for future applications, so we suggest that the CVD setup with a vertical vapor flow could potentially be used for the synthesis of highly uniform MoS₂ instead of the horizontal vapor flow we use now.

Fig. 1 MoS₂ fin-shaped field effect transistors. (a) Schematic plot of a MoS₂ fin-shaped field effect transistor. (b) A top-view SEM image of a MoS₂ fin-shaped field effect transistor. White lines in the center indicate the cutting position for a cross-section TEM inspection. (c) A cross-section TEM image of a MoS₂ fin-shaped field effect transistor. (d) A high resolution TEM image of a MoS₂ fin structure, showing the MoS₂ thickness of about 3 nm (∼5 layers) in the MoS₂ fin-shaped field effect transistors.

During the fabrication process of the MoS₂ fin-FET, we purposefully combine a traditional implantation technique into our process to make both n-type and p-type MoS₂ conduction channels possible in the same 2D layered material. The mechanism enabling the acquisition of both the n- and p-type MoS₂ conduction channel is proposed below. According to our previous experience of the Si-TMD contact, highly doped Si directly contacting with TMD materials is possible to adjust the channel chemical potential with respect to the original level. Owing to the dramatic formation of band bending in MoS₂, the MoS₂ Fermi level is effectively close to the conduction band by the n⁺ Si contact or the valence band by the p⁺ Si contact. The band diagrams for n-type and p-type contacts on the OFF state are separately shown in Fig. 2(a) and (c), which indicate that the electron and hole in two cases are blocked due to the energy barrier ϕ_n and ϕ_p respectively. On the contrary, the electron and the hole in both cases can transport as conducting carriers in the ON state while gate voltages are applied in the positive direction for the n-type contact and in the negative direction for the p-type contact as shown in Fig. 2(b) and (d), in which the gate voltage must at least overcome the energy barrier (i.e. V_th). In our experiments, since we selectively implant Si contacts as n⁺ Si and p⁺ Si for the seed to grow the MoS₂ film on a wafer/chip, both n-type and p-type MoS₂ conducting channels are expected to be simultaneously obtained in a run of the fabrication process.

Fig. 2 Band diagrams of highly doped Si contacts with MoS₂ for p-type and n-type channel conduction. (a and b) MoS₂ contacts with n⁺ Si while conduction is OFF state and ON state for n-type channel conduction. (c and d) MoS₂ contacts with p⁺ Si while conduction is OFF state and ON state for p-type channel conduction.

Electrical characterization is performed to confirm the feasibility of the proposed model. The typical measured output characteristic (I_d–V_d) curves and transfer characteristic (I_d–V_g) curves for n-type and p-type MoS₂ channels are shown in Fig. 3. The measured current is increased as the negative gate voltages increase in the case of the p-type Si contact while the current is increased as the positive gate voltages increase in the case of the n-type Si contact. The corresponding output characteristics of n-type and p-type MoS₂ fin-FETs are shown in Fig. 3(a) and (b), respectively. The slightly nonlinear I_d–V_d curves indicate that the hetero interface between MoS₂ and doped Si still has contact issues due to the presence of the van der Waals gap or other contaminations respectively increasing specific contact resistance (R_c) and resistance under contact (R_sh) while using the transfer length model (TLM).^25,26 Even though the quantum limit of the metal/2D material contact hasn’t been achieved, methods such as further thermal annealing or surface modification of MoS₂ have been proposed in order to achieve better contact.^27,28Fig. 3(c) and (d) show the transfer characteristics of p-type and n-type MoS₂ fin-FETs with a device current ON/OFF ratio of approximately 10⁶ at V_d = 1 V. The result of electrical characterizations evidenced that MoS₂ shows p-type behavior as grown from the p⁺ Si contact while MoS₂ is an n-type channel as synthesized from the n⁺ Si electrodes.

Fig. 3 Typical electrical characteristics of the MoS₂ fin-shaped field effect transistors. Current versus drain voltage curves at different gate voltages for (a) p-type and (b) n-type operation. Current versus gate voltage curves at different drain voltages for (c) p-type and (d) n-type operation. The p-type behavior is due to the MoS₂ film growth from the p⁺ Si contact while the MoS₂ film is an n-type channel as synthesized from the n⁺ Si contact.

Fig. 4(a) and (b) show the distributions of 20 typical devices’ ON-current (I_on) and threshold voltages (V_th) for n-type and p-type MoS₂ fin-FETs in an identical chip. I_on and OFF-current (I_off) are normalized by the whole channel width (fin circumference) instead of the fin size only. Most of the devices possess a symmetric V_th well while I_on reaches to around 50 μA μm⁻¹ for both n-type and p-type MoS₂ fin-FETs with V_d = 1 V. The I_off for both cases is very low, which is close to 10⁻⁵ μA μm⁻¹. The corresponding measured transfer characteristic (I_d–V_g) curves for p-type and n-type MoS₂ fin-FETs are provided in Fig. S4 and S5 in the ESI.† Note that there are variations in threshold voltage which we think are caused by charges originating from dielectric materials when we deposit HfO₂ or Al₂O₃ on top of MoS₂ for the top-gate structure. A comparison of p-type MoS₂ performance using our strategy and other methods in the literature is summarized in Table 1.^21,23,29,30 The field effect mobility (μ) is extracted from I_d–V_g through calculating the approximation equation

in the linear region with V_d = 0.1 V. The gate capacitance we used is only the consideration of top gate capacitance (about 97.5 pF) because top gate capacitance is larger than the bottom gate and coupling capacitance between the top and the back gate in our device structure. This will lead to slightly overestimated mobility in our calculation. It should be noted that μ values obtained (10 cm² V⁻¹ s⁻¹) are higher at most by 30% distinct from the estimation which treats the FETs as planar structures if the approximate capacitance of fin-oxide is involved in our calculation. It should also be noted that the ON current density is around 50 μA μm⁻¹ while normalized by dividing current by total width including the fin. If one considers the footprint for the fin size (the channel length is about 30nm in top view) only and takes the effective capacitance of fin-oxide into account, the effective current density is even larger (∼500 μA μm⁻¹) than what we acquired now.

Fig. 4 Typical (a) on current (I_on) and off current (I_off) and (b) threshold voltage (V_th) distribution for 10 n-type and 10 p-type MoS₂ fin-shaped field effect transistors in identical chips.

Table 1 A comparison of p-type MoS₂ performance, process technology and the structure made using our strategy and other methods

	p-Type silicon [ref. 23]	AlCl3 [ref. 30]	MoOx buffer [ref. 21]	Nb doping [ref. 29]	This work
ON-current density (μA μm^−1)	150	21	0.13	1	50
					∼500 (effective)
ON–OFF ratio	10^6	10^7	10^4	10^4	10^6
Mobility (cm^2 V^−1 s^−1)	—	132	—	6.7	10
Sample preparation	CVD	Exfoliation	Exfoliation	Exfoliation	CVD
Channel structure	Planar	Planar	Planar	Planar	Fin-shaped

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Since a dual gate structure (top and bottom gates) is designed in our MoS₂ fin-FETs for better control, the back gate is used to adjust the threshold voltages in both n- and p-type MoS₂ fin-FETs. Note that MoS₂ on the gate oxide in the fin and planar structure is about 100 nm and 30 nm respectively (see Fig. 1(a) and (c)). The back gate can simultaneously tune both regions in MoS₂ to produce a unitary phenomenon. By controlling the back gate bias, we can correct device variations or dynamically configure a device as a high-performance or low energy consumption device in order to achieve higher speed and/or lower power applications. Fig. 5(a) and (b) show the results that back gate voltage can effectively shift the threshold voltages and the comparison of the V_th shift by the back gate for n- and p-type MoS₂ fin-FETs is displayed in Fig. 5(c). We can clearly observe from Fig. 5(c) that the threshold voltage is adjustable for the tuning of the 0.5 V shift per back-gate bias applied (0.5 V/1 V) based on the back-gate control. However, the separated back gate for n- and p-type MoS₂ fin-FETs is needed to selectively control individual devices in order to achieve adjustable device performance in the future.

Fig. 5 Transfer characteristics for (a) p-type MoS₂ fin-shaped field effect transistors and (b) n-type MoS₂ fin-shaped field effect transistors under different back gate voltage control. (c) Threshold voltage (V_th) dependence of the back gate bias for p- and n-type MoS₂ fin-shaped field effect transistors.

A complementary MoS₂ inverter for basic integrated circuit complementary device applications was demonstrated by integrating one n-MoS₂ fin-FET and one p-MoS₂ fin-FET connected in series without back-gate voltage. The device schematic is shown in Fig. 6(a). The transfer characteristic curves of the CMOS2 inverter as a function of V_DD are shown in Fig. 6(b), which exhibits a clear inversion signal with high V_out and low V_in. From the result, it is indicated that the noise margin to get reliable data is V_DD larger than 0.1 V. The peak dc voltage gain, |∂V_out/∂V_in|, of the CMOS2 fin-FET inverter is measured to be 20 times larger at a supply voltage V_DD of 3 V with a full width at half maximum (FWHM) of 0.15 V, as shown in Fig. 6(c). Compared to hetero material (MoS₂/WSe₂) based complementary inverters that could achieve a DC gain higher than 100,³¹ the performance of our inverters still has room for improvement. In the case of complementary inverters constructed by the same doped 2D materials (WSe₂/WSe₂, MoTe₂/MoTe₂), our work shows comparable results of the DC gain.^32,33 Mostly, the CMOS2 inverter we demonstrated is superior to inverters based on MoS₂ reported.^34,35Table 2 shows a comparison of the device performance and the material structure between this work and devices made from others.^31,36–39

Fig. 6 MoS₂ fin-shaped field effect transistor inverters. (a) Schematic plot of a MoS₂ fin-shaped field effect transistor inverter. (b) Voltage-transfer characteristics of the complementary MoS₂ inverters at different V_DD. (c) Direct-current voltage gain of the inverter at different supply voltages.

Table 2 A comparison of the inverter device performance and the material structure between this work and devices made by others

	[Ref. 31]	[Ref. 36]	[Ref. 37]	[Ref. 38]	[Ref. 39]	This work
DC gain	110@2 V	25@5 V	38@2 V	13.7@2 V	60@5 V	22@3 V
	80@2.8 V		33@3 V
Sample preparation	CVD	CVD	Exfoliation	Exfoliation	CVD	CVD
Channel materials and structure	Planar MoS2 + WSe2	Planar WSe2	Planar WSe2	Planar MoS2 + WSe2	Planar MoS2	Fin-shaped MoS2

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We have demonstrated the chip-scale growth of continuous layered MoS₂ fully covered on an SiO₂ fin-shaped structure and integration of n-type and p-type MoS₂ by using the traditional implantation technique to exhibit complementary MoS₂ fin-shaped field effect transistors. The highly doped n⁺ and p⁺ Si as the nucleation seeds to grow MoS₂ can induce Fermi level tuning and successfully make MoS₂ with n- and p-type operations possible. These MoS₂ fin-shaped field effect transistors typically show a few tens μA μm⁻¹ in average ON current and around 10⁶ in current ON/OFF ratio. Accordingly, the complementary MoS₂ inverter is displayed with more than 20 high voltage gain. A better understanding to grow MoS₂ on higher fin oxide structures or uneven topography is an interesting task to figure out the growth mechanism behind this. The results are fascinating and promising for the future development of full wafer availability in stacked 3D integrated circuit applications based on 2D materials.

Conflicts of interest

The authors declare no conflicting financial interest.

Acknowledgements

This work was supported by the National Science Council, Taiwan under contract No. MOST 105-2112-M-003-016-MY3. This work was also in part supported by the National Nano Device Laboratories. Y.-W. Lan, P.-C. Chen, Y.-Y. Lin, Y.-L. Tu and K.-S. Li fabricated the devices and carried out OM, SEM, TEM, Raman measurements and the electrical characterization. M.-Y. Li and L.-J. Li synthesized the 2D materials. Y.-W. Lan, M.-C. Chen, F.-L. Yang and K.-S. Li supervised the study. Y.-W. Lan, M.-C. Chen and K.-S. Li analyzed the data and wrote the paper with significant inputs from all authors. All authors have read and approved the manuscript. All authors discussed the results and commented on the manuscript.

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Footnote

† Electronic supplementary information (ESI) available. See DOI: 10.1039/c8nh00419f

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