Promising ultra-short channel transistors based on OM₂S (M = Ga, In) monolayers for high performance and low power consumption

Abstract

It is hoped that two-dimensional (2D) semiconductors overcome the short channel effect and continue Moore's law. However, 2D material-based ultra-short channel devices still face the challenge of simultaneously achieving high-performance (HP) and low-power (LP) consumption. Here, we theoretically designed monolayer OM₂S (M = Ga, In)-based metal–oxide–semiconductor field-effect transistors (MOSFETs), considering the gate length from 1 to 5 nm, doping concentration and underlap structure. We found that in HP (LP) applications, the on-state current exceeds 1000 (500) μA μm⁻¹ under a 1 nm (2 nm) gate length, surpassing the needs of the International Technology Roadmap for Semiconductors (ITRS) in 2028. The subthreshold swing is close to the Boltzmann tyranny (60 mV dec⁻¹) even as the gate length shrinks to 2 nm. The energy-delay product is two orders lower than 1.02 × 10⁻²⁸ J s μm⁻¹, indicating extraordinary high-speed manipulation and low-energy expending. Therefore, monolayer OM₂S has great application in ultra-short scale devices with HP and LP consumption, and can be taken as a candidate to extend Moore's Law.

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1. Introduction

Currently, the size of an electronic device is constantly reduced to meet the needs of miniaturization and highly integrated development. However, the short channel effects and high power consumption restrict the downscaling of traditional device dimensions.^1–3 Thus, it is pivotal to probe promising channel materials for further continuation of Moore's Law. Recently, it is hoped that two-dimensional (2D) materials replace silicon for highly integrated devices because of their particular intrinsic characteristics, such as atomic thickness, dangling bonds-free surfaces, and high carrier mobility.^4–8

Group-III chalcogenides possess remarkable electrical and optical features, which can be broadly used in field-effect transistors (FETs), photodetectors and gas sensors.^9–13 For example, the responsivity and on/off ratio of back-gated GaS-based FETs are ∼6.4 A W⁻¹ and ∼170, respectively.¹⁴ The carrier mobilities of atomically thin InSe were discovered to outnumber 10³ cm² V⁻¹ s⁻¹ (at room temperature) and 10⁴ cm² V⁻¹ s⁻¹ (at liquid-helium temperature), respectively.¹⁵ InS-based devices demonstrate native n-type performance, accompanied by a high on/off current ratio (10³).¹⁶ Zhang et al. used the chemical vapour deposition (CVD) method to fabricate a Janus MoSSe monolayer, and its atomic layers are arranged as S–Mo–Se, which induces an intrinsic piezoelectric response and a high catalytic activity for the hydrogen evolution reaction.¹⁷ Motivated by this study, 2D Janus materials and their performance have also been studied extensively.^18–30 Among them, the Janus monochalcogenides have received much attention, such as Ga₂SSe, GaInS₂, In₂SSe, Sn₂SeS and SnGeS₂.^25–29,31 Different from Janus transition metal dichalcogenides, Janus monochalcogenides based on GaS include GaInS₂, Ga₂SSe and GaInSSe, which consist of double Ga–Ga (In) metal layers sandwiched between S and S (Se) chalcogen layers.^25,31 For example, Kandemir et al. found that the Janus In₂SSe is a robust direct gap semiconductor under tolerable strain.²⁶ Janus Sn₂SeS inherits the orthorhombic structure of the SnS monolayer and has large piezoelectric properties and high carrier mobility, especially the in-plane piezoelectric coefficient (up to 179.37 pm V⁻¹) is many times higher than that of MoS₂ (3.73 pm V⁻¹).³⁰

More recently, gallium- or indium-based Janus monochalcogenides have been studied.^28,32–34 Liu et al. proposed a class of Janus group-III monochalcogenide OM₂S (M = Ga, In) monolayers and reported that they are thermally, dynamically, and mechanically stable 2D materials.³² Moreover, the electron mobility of monolayer OIn₂S exceeds 3 × 10³ cm² V⁻¹ s⁻¹, which is higher than those of InSSe (884.8 cm² V⁻¹ s⁻¹), InSe (943.3 cm² V⁻¹ s⁻¹), MoSSe (52.27 cm² V⁻¹ s⁻¹) and WSSe (120.88 cm² V⁻¹ s⁻¹).^23,33 Monolayer OGa₂S possesses a direct band structure and strong optical absorption.³⁴ We would like to point out that gallium-based or indium-based monochalcogenides have not been synthesized to date. OM₂S monolayers have good stability, high electron mobility and suitable direct band gaps, which make them promising channel material candidates for further continuation of Moore's law. However, the investigation of ternary group-III chalcogenides is mainly concentrated on their electronic, optical, and magnetic characteristics.^{25,26,35–37} Therefore, the transport properties of monolayer ultra-short scale OM₂S devices are still worth studying.

Here, the transport characteristics of ultra-short-channel OM₂S metal–oxide–semiconductor field-effect transistors (MOSFETs) were systematically investigated. To further expand the application of devices in high-performance (HP) and low-power (LP) consumption, the doping concentration of the electrode region is adjusted and the underlap length is scaled. The calculation results reveal that the on-state current for a 1 nm OM₂S device reaches 1000 μA μm⁻¹, which exceeds the standard of HP applications (900 μA μm⁻¹). Moreover, the on-state current for an OM₂S device with a 2 nm gate length is about two times higher than that for the LP standard, which is 295 μA μm⁻¹. This work is expected to provide a new opportunity for realizing ultra-short scale electronic devices with HP and LP consumption simultaneously.

2. Methods

Geometric optimization, band structure, and band-decomposed charge-density analyses were carried out using the Vienna ab initio simulation package (VASP) based on density functional theory (DFT).³⁸ The plane-wave cutoff was set as 550 eV. The energy and force convergence tolerances were set to 10⁻⁵ eV and 0.01 eV Å⁻¹, respectively. A 13 × 13 × 1 k-point mesh was used for the sampling in the reciprocal space.

The transfer characteristics, densities of states, transmission spectra, and local density of states were determined by the combination of DFT and the non-equilibrium Green's function, which was implemented in the Atomistix ToolKit (ATK).³⁹ According to the formula of Landauer–Bűttiker, the drain current (I_ds) can be computed as:

where T(E), f_d(f_s) and μ_d(μ_s) stand for the transmission coefficient, Fermi–Dirac distribution function and electrochemical potential of the drain (source), respectively.

For self-consistency of the electronic structure, we set a real space mesh cutoff of 135 Ha and Monkhorst–Pack k meshes for OGa₂S and OIn₂S MOSFETs of 1 × 21 × 162 and 1 × 21 × 148, respectively. The temperature was set as 300 K. PseudoDojo optimized norm-conserving pseudopotentials and a medium basis set were used. In addition, the Neumann, periodic, and Dirichlet boundary conditions were applied in the directions of x, y, and z, respectively. In addition, the exchange–correlation interaction was performed using the generalized gradient approximation and the Perdew–Burke–Ernzerhof functional.^40,41

3. Results and discussion

The geometric and electronic characteristics of monolayer OM₂S (M = Ga, In) are shown in Fig. 1. These optimized lattice parameters are a = b = 3.375 Å and a = b = 3.688 Å for monolayer OGa₂S and OIn₂S, respectively. This is very consistent with the previous reports.³² In Fig. 1(a), monolayer OM₂S is a sandwich structure with the S and O atoms locating both the side layer and two M atoms as the middle layer. The difference between the upper and lower layers demonstrates that OM₂S is a ternary structure. Moreover, the M–S, M–O, and M–M bonds are all connected in the form of covalent bonds. Monolayer OGa₂S and OIn₂S have similar band-decomposed charge-density distributions, which are relevant to the conduction band minimum (CBM) and the valence band maximum (VBM). The electron wave function is located at the vicinity of O, S, and M atoms at the CBM. The hole wave function is mostly located near the S atom. The band-decomposed charge density distributions of OM₂S are shown in Fig. S1 of the ESI.†

Fig. 1 (a) Top view and side view of the OM₂S monolayer, and the band-decomposed charge density relevant to the CBM and VBM for OGa₂S. Dashed rhombus stands for the unit cell. (b) A device model of dual-gate monolayer OM₂S MOSFETs. t_ox and t_ch are the dielectric thickness and the channel material thickness, respectively. (c) Projected electronic structures and density of states for the OGa₂S monolayer. (d) Transfer characteristics of n-type and p-type OGa₂S MOSFETs with various L_g values. The doping concentration in the electrode region is 3 × 10¹³ e cm⁻², and V_ds is 0.64 V. The gray and orange dashed lines stand for ITRS off-state current standards for HP and LP applications, respectively.

Fig. 1(c) and Fig. S1(a) of the ESI† show the band structures of monolayer OGa₂S and OIn₂S, both of them are direct bandgap semiconductors. The bandgap (E_g) of OGa₂S and OIn₂S is 1.27 eV and 1.05 eV, respectively. Both the CBM and VBM of them are situated at Γ. Moreover, we can know from ESI Fig. S2† that the states around the CBM of OM₂S are mostly devoted to M_s, M_p, and S_p orbitals. The VBM of OGa₂S is mainly offered by S_p orbitals and a little by Ga_p orbitals, but the VBM of OIn₂S is provided by S_p orbitals. It is worthy to note that the CBM and VBM of OM₂S have similar energy dispersion relationships along the armchair and zigzag directions, and this work only uses the armchair direction as the transport direction for brevity.

Fig. 1(b) shows the constructed double-gate (DG) monolayer OM₂S MOSFETs. The transfer characteristics of the DG and single-gate (SG) OGa₂S MOSFETs are shown in Fig. S3 and elaborated in the ESI.† Considering that OGa₂S has two different chalcogen surfaces, we constructed two SG devices, where SG_O and SG_S represent the cases where the gate is added to the oxygen and sulfur terminals, respectively. The off-state current (I_off) of the SG_O device is difficult to meet the high-performance (HP) requirement of the ITRS 2028 level. The LP on-state current (I_on) of the DG device (1300.2 μA μm⁻¹) is about 10 times larger than that of the SG_S configuration. In addition, the subthreshold swing (SS) of the DG OGa₂S MOSFET (63.6 mV dec⁻¹) is smaller than that of its SG counterpart (73.0 mV dec⁻¹). Since the DG monolayer OGa₂S MOSFETs have better gate control capability, the transport performances are better than that of the SG configuration, so we used the dual-gate configuration instead of the SG model in this work. The intrinsic and doped OM₂S monolayers act as channels and electrodes, respectively. In previous theoretical reports, similar electrode structures have been widely used to study the performance of devices including GeSe, BiN, β-TeO₂ and GaN MOSFETs.^3,42–49 For example, Wang et al. studied the performance limit of the transport characteristics of monolayer planar GaN transistors with the heavy doping hypothesis as the electrodes, and demonstrated the feasibility of the design of the electrode structure by studying the contact characteristics of the active region.⁴⁹

To prevent the interactions among neighboring units, the vacuum regions of OGa₂S and OIn₂S normal to the surface are found greater than 20 Å. The equivalent dielectric layer thickness is 0.41 nm and the bias voltage (V_ds) of sub-5 nm devices is 0.64 V. On the basis of HP and LP standards for ITRS 2028 horizon, the I_off should be 0.1 μA μm⁻¹ and 5 × 10⁻⁵ μA μm⁻¹, respectively. I_on corresponds to the drain current with the on-state gate voltage (V_g,on). V_g,on can be calculated using the following formula: V_g,on = V_g,off ± V_ds,⁴⁶ where V_g,off is the off-state voltage. The underlap (UL) stands for the undoped channel zone between the source and gate or the drain and gate. In this work, the symmetric length of underlap (L_UL) is used. Therefore, the channel length (L_ch) can be defined as L_ch = L_g + 2L_UL, where L_g is the gate length. We would like to point out that this work is only intended to predict the performance limit of OM₂S MOSFETs with an ultra-short channel. Considering the computational cost and resources, the transport properties of the electron–phonon interaction are not considered.

The transfer characteristics of n-type and p-type OM₂S MOSFETs under various gate lengths are shown in Fig. 1(d) and ESI Fig. S4.† OGa₂S MOSFETs possess larger I_ds than that of OIn₂S MOSFETs. With the increase of gate length both n-type and p-type MOSFETs demonstrate the retention of saturation current (I_sat), but the leakage current decreases gradually. In addition, when the gate length is 5 nm, n-type OM₂S and p-type OIn₂S devices can satisfy the I_off standard of ITRS in LP applications. For n-type MOSFETs, OIn₂S can fulfill the I_off needs for ITRS 2028 horizon in HP devices when the gate length shrinks to 2 nm. However, the minimum gate length for satisfying this standard is 3 nm for OGa₂S n-MOSFETs. More strikingly, the I_on values of these two n-type devices with 3 nm and 5 nm gate lengths are more than 2000 μA μm⁻¹ and 1000 μA μm⁻¹, respectively, far exceeding HP and LP standards. The I_ds of 5 nm OGa₂S p-MOSFETs approaches the I_off standards of LP devices at a gate voltage of 1.4 V. The maximum I_ds of sub-5 nm OIn₂S p-MOSFETs is below 1 × 10³ μA μm⁻¹ as the gate voltage ranges 0.5–1.4 V. Although OGa₂S has higher I_ds, its leakage current is larger than that of OIn₂S. Therefore, it is necessary to find a way to reduce the leakage current while maintaining other excellent performances. For simplicity, we take OGa₂S MOSFETs as an example for the following study, and the results of OIn₂S MOSFETs are presented in the ESI.† Moreover, considering the excellent performance of n-type MOSFETs, we focus on the case of n-type OM₂S.

One of the critical factors affecting the transport properties of devices is the doping concentration, which determines the concentration of injected carriers. Therefore, it is necessary to explore the doping concentration influence in the electrode region. The I_ds values of OGa₂S MOSFETs with gate lengths of 1 nm, 3 nm, and 5 nm changing with the doping concentration and gate voltage are shown in Fig. 2(a). Compared with the cases of 3 nm and 5 nm L_g, it is more difficult to restrain the leakage current of 1 nm OGa₂S MOSFETs owing to their severe short channel effect. When the doping concentration is lower than 8 × 10¹³ e cm⁻², the OGa₂S MOSFETs with 3 nm gate length can satisfy the I_off standard for HP applications. For the OGa₂S case with 5 nm L_g, the HP (LP) off-state current standard can be satisfied when the doping concentration ranges from 1 × 10¹³ to 1 × 10¹⁴ (5 × 10¹³) e cm⁻². V_g,off increases gradually with the doping concentration increases, which is the result of the enhancement of carrier concentration.

Fig. 2 (a) The color contour map of the source–drain current at L_g = 1 nm, 3 nm, and 5 nm for monolayer OGa₂S MOSFETs. The gate voltage range is −1.0–0 V, and the doping concentration range is 5 × 10¹²–1 × 10¹⁴ e cm⁻². (b) The SS and g_m of the monolayer OGa₂S MOSFETs as a function of doping concentration and L_g. (c) The densities of states and (d) transmission spectra of 4 nm OGa₂S MOSFETs with different doping concentrations.

To further assess the influence of doping concentration variation on the gate controllability of the OGa₂S MOSFETs with different gate lengths, the subthreshold swing (SS) and transconductance (g_m) are extracted from the transfer characteristics (see Fig. S5 of the ESI†). SS can be obtained from the following formula: ,⁴⁷ representing the gate voltage required by each order of magnitude change for the current in the subthreshold region. Small SS corresponds to a strong gate control capability.⁴⁷Fig. 2(b) shows that SS decreases sharply with the decrease of doping concentration when L_g is less than 3 nm. The SS of OGa₂S MOSFETs with 1 nm L_g is decreased by more than 500 mV dec⁻¹ when the doping concentration decreases from 1 × 10¹⁴ to 5 × 10¹² e cm⁻². However, it only decreases from 65.9 to 61.7 mV dec⁻¹ for the 5 nm OGa₂S MOSFETs. On the other hand, for the superthreshold region, the gate control capability can be characterized by g_m (g_m = dI_ds/dV_g). A larger g_m corresponds to a larger current value, which is advantageous to obtain a large on-state current.⁵⁰Fig. 2(b) also shows that the g_m of devices with different gate lengths exhibits a similar increasing trend. For example, the g_m values of 1 nm and 5 nm devices are 1.55 × 10³–1.46 × 10⁴ μS μm⁻¹ and 2.04 × 10³–2.04 × 10⁴ μS μm⁻¹, respectively. The above analysis shows that SS and g_m should be a trade-off in the selection of doping concentration.

To reveal the influence mechanism of the doping concentration on gate modulation, the density of states (DOS) and transmission spectra are shown in Fig. 2(c) and (d). The DOS and transmission spectra exhibit an increasing behavior with the increase of doping concentration. The large DOS in the bias window proves that there are a large number of electrons in the channel. On the basis of the above Landauer–Bűttiker formula, the current can be obtained by integrating the transmission spectrum coefficient inside the bias window. A larger transmission corresponds to a higher current. Thus, the g_m of the device with a 1 × 10¹⁴ e cm⁻² doping concentration is larger than those of other doping concentrations, which can be attributed to the large transmission spectrum. To further explain the mechanism of SS changes with the doping concentration, Fig. S6 and S7 of the ESI† show the transmission spectra and spectral current of the 2 nm and 3 nm OGa₂S MOSFETs with different doping concentrations. At V_g = −0.6 V, the 3 nm OGa₂S MOSFETs show a lower transmission possibility within the bias window than that of 2 nm devices, thus it is easier for the former to approach the off-state. Fig. S7† shows that compared with the 2 nm devices, the 3 nm OGa₂S MOSFETs have a larger difference in the spectral current, resulting in a lower SS. Moreover, with the decrease of doping concentration, the difference of spectral current increases gradually and thus SS decreases.

In addition, adding UL structures is another effective way to reduce leakage current. The reason is that the transmission possibility (T(E)) is reduced by increasing the channel barrier width (Λ).⁵¹ Thus, the effect of UL length on the characteristics of devices with different gate lengths is systematically shown in Fig. 3. As known from Fig. 3(a), with an increase in L_g, the effect of UL on the transfer characteristics decreases. At the same value of L_g, the leakage current is suppressed to some extent with the increase of UL. For L_g = 1 nm, the leakage current is significantly decreased by utilizing the strategy of UL. When L_UL is larger than 1 nm, the value of I_off can approach the HP standard of ITRS in 2028. However, for the device with 3 nm L_g, I_off reaches the LP standard of ITRS in 2028 using 1 nm UL. Moreover, as the increase of L_UL, V_g,off is almost constant for the MOSFETs possessing a gate length of 5 nm. To intuitively evaluate the influence of L_UL and L_g on device transport characteristics, Fig. 3(b) shows SS and I_on, which are extracted from the transfer characteristics (see Fig. S8 of the ESI†). The results show that SS is mainly localized between 60 and 80 mV dec⁻¹. For the HP (LP) applications, I_on ranges from 299.3 (68.2) μA μm⁻¹ to 2618.0 (1587.6) μA μm⁻¹. The UL length less than 2 nm is beneficial for sub-5 nm OGa₂S MOSFETs to achieve higher I_on. For instance, the I_on values of 1 nm OGa₂S MOSFETs with 2 nm and 3 nm UL lengths are 1032.8 and 694.1 μA μm⁻¹, respectively. The SS of the device with 2 nm L_g is 68.5 mV dec⁻¹ when the L_UL is equal to 4 nm, which is lower than that of 1 nm UL (106 mV dec⁻¹). Therefore, the gate capability of the subthreshold region can be improved by increasing the UL length.

Fig. 3 (a) The color contour map of the source–drain current at L_g = 1 nm, 3 nm, and 5 nm for monolayer OGa₂S MOSFETs. The gate voltage range is −1.0–0 V, and the UL range is 1–4 nm. (b) The SS and I_on of the monolayer OGa₂S MOSFETs as a function of L_UL and L_g. Spatially resolved local DOS of the 3 nm OGa₂S MOSFETs with various UL lengths at (c) the off-state and (d) the on-state. μ_S and μ_D stand for the electrochemical potentials of the source and drain, respectively.

To drill deeper into the modulation mechanism of UL, Fig. 3(c) and (d) show the on- and off-state local DOSs of a 3 nm gate-length OGa₂S device without/with UL configuration. The channel barrier (Φ_B) is delimited as the vertical dimension between the lowest location energy of the conduction band and the Fermi energy of the source. In the off-state, the drain current can be mainly composed of the tunnel current (I_tunnel), which is defined as:⁴⁶

Thus, the large Φ_B and Λ are key factors to obtain a small I_tunnel. In Fig. 3(c), we can know that the Φ_B of the device without UL is 0.26 eV. The device with 1 nm UL possesses lower Φ_B (0.18 eV), which is not conducive to inhibiting the leakage current. However, the Λ of the device with 1 nm UL is wider, easy to obtain a lower leakage current. With the increase of gate voltage, both the conduction band and valence band move down, resulting in a decrease of Φ_B. In Fig. 3(d), the Φ_B of the device without/with UL configuration for the on-state can be reduced to 0 eV, demonstrating large I_ds. However, the device with 1 nm UL has more electrical states in the bias window than the device without UL. Therefore, I_on increases when 1 nm UL is used.

As mentioned above, the LP devices have higher requirements for I_off than that of HP devices. For the sub-3 nm devices with large leakage current, we used a doping concentration of 1 × 10¹³ e cm⁻² to improve the performance of LP applications. In Fig. 4, compared with the 3 × 10¹³ e cm⁻² doping concentration, the devices with a 1 × 10¹³ e cm⁻² doping concentration has higher I_on and lower SS under the same L_g and L_UL. For example, when L_g and L_UL are equal to 3 nm and 2 nm, the I_on values of the OGa₂S (OIn₂S) MOSFETs with 3 × 10¹³ and 1 × 10¹³ e cm⁻² doping concentrations are 632.1 (702.61) and 805.2 (865.3) μA μm⁻¹, respectively. With the increase of L_UL, I_on first increases and then decreases, which is mainly because of the degradation of gate control capability in the superthreshold zone. For devices with a gate length of 2 nm, the maximum on-state current is reached when L_UL is equal to 2 nm. It is worthy to note that both OGa₂S and OIn₂S MOSFETs can approach the I_on standard of ITRS low-power applications when L_g is scaled to 2 nm. Moreover, the maximum on-state current for the OM₂S device with a 2 nm gate length can exceed 500 μA μm⁻¹ and the value is two times higher than that of the LP standard.

Fig. 4 The I_on and SS of monolayer (a and b) OGa₂S and (c and d) OIn₂S MOSFETs at different L_UL and L_g lengths. Red and blue cuboids represent the doping concentrations of 3 × 10¹³ and 1 × 10¹³ e cm⁻², respectively.

In the following, we study the performance of switching speed and energy consumption for the ultra-short-channel OM₂S MOSFETs. It is known that the intrinsic delay time (τ) can be taken as a critical parameter to characterize the conversion speed of logic devices, which can be described as ,⁵² where Q_on and Q_off represent the Mulliken charge of the channel at the on-state and off-state, respectively, and W is the width of the channel. Fig. 5(a) shows that the τ values of sub-5 nm OGa₂S and OIn₂S MOSFETs are within the range of 0.027–0.039 ps, lower than the requirement of ITRS in 2028 for the HP (0.423 ps) applications. In Fig. 5(b), the sub-5 nm OGa₂S and OIn₂S MOSFETs exhibit ultra-low τ values of 0.04 and 0.119 ps, which are far below the LP applications standard (1.497 ps). This feature indicates that the sub-5 nm OM₂S MOSFETs have the advantage of fast switching speed.

Fig. 5 PDP and I_on for monolayer OM₂S and other 2D n-MOSFETs^49,53–58 as functions of τ in HP (a) and LP (b) applications. The black dotted line represents the energy-delay product (EDP) standard of the ITRS 2028 horizon (1.02 × 10⁻²⁸ J s μm⁻¹ for HP and 4.18 × 10⁻²⁸ J s μm⁻¹ for LP).

The energy consumption characteristics can be evaluated by the switching-energy cost of power dissipation (PDP), which is calculated as .⁵² In Fig. 5, the PDP values of sub-5 nm OGa₂S (0.026–0.06 fJ μm⁻¹) and OIn₂S (0.023–0.057 fJ μm⁻¹) MOSFETs fulfill the ITRS needs for HP (0.24 fJ μm⁻¹) applications. The OGa₂S and OIn₂S MOSFETs present lower PDP values of 0.013–0.048 fJ μm⁻¹ and 0.017–0.054 fJ μm⁻¹ compared with the target of LP (0.28 fJ μm⁻¹) applications, demonstrating an extremely low switching-energy cost for the OM₂S MOSFETs.

To express the relationship between τ and PDP, we calculated the energy-delay product (EDP) defined as the expression EDP = τ × PDP.⁴⁴ The EDP of the sub-5 nm OM₂S MOSFETs is varied from 8.28 × 10⁻³¹ to 2.22 × 10⁻³⁰ J s μm⁻¹ in HP applications and 8.8 × 10⁻³¹ to 3.22 × 10⁻³⁰ J s μm⁻¹ in LP applications. The detailed comparations with other sub-5 nm n-type MOSFETs are listed in Fig. 5. It can be found that monolayer OM₂S MOSFETs possess lower EDP for HP and LP applications than those of MoS₂,⁵³ MoSi₂N₄,⁵⁴ InP,⁵⁵ MoTe₂,⁵⁶ and GaN.⁴⁹ For example, in HP applications, the EDP value of OGa₂S MOSFETs with 3 nm L_g can be 1.22 × 10⁻³⁰ J s μm⁻¹, less than those of MoS₂ (5.77 × 10⁻²⁹ J s μm⁻¹), MoSi₂N₄ (1.63 × 10⁻²⁹ J s μm⁻¹), and GaN (3.19 × 10⁻²⁸ J s μm⁻¹). In the LP applications, when L_g is 1 nm, the EDP values of OGa₂S and OIn₂S MOSFETs are 1.38 × 10⁻³⁰ and 2.02 × 10⁻³⁰ J s μm⁻¹, respectively, lower than those of MoS₂ and MoSi₂N₄. Although the EDP of OM₂S is slightly inferior to those of As,⁵⁷ Sb,⁵⁷ and InSe⁵⁸ cases, the I_on of OM₂S is significantly superior to the latter. Therefore, both OGa₂S and OIn₂S MOSFETs possess extraordinary high-speed manipulation and low-energy expending, which are beneficial for the HP and LP applications.

4. Discussion

To check whether our devices meet IRDS standards, we took the 12 nm n-type OGa₂S MOSFETs as an example to further assess the performance of OM₂S MOSFETs with a V_ds value of 0.65 V, and the I_off value is specified to 0.01 μA μm⁻¹ for HP and 1 × 10⁻⁴ μA μm⁻¹ for LP. Fig. S9 and Table S1† show that the OGa₂S MOSFETs possess high I_on (2570.7 μA μm⁻¹ for HP and 2279.8 μA μm⁻¹ for LP), far exceeding the required current criteria (1979 μA μm⁻¹ for HP and 1336 μA μm⁻¹ for LP) of IRDS in 2028. Moreover, other performance parameters of OGa₂S MOSFETs, including SS, τ and PDP, also meet IRDS standards.

5. Conclusion

In summary, we designed an ultra-short-channel double-gate OM₂S MOSFETs and systematically investigated the effect of doping concentrations and UL length modulations on the transport properties. The n-type OM₂S MOSFETs have a larger saturation current and a smaller leakage current than those of the p-type OM₂S MOSFETs. The drain current of the OGa₂S case was higher than that of the OIn₂S case. Moreover, for the OM₂S MOSFETs with 1 nm gate length, the on-state current can reach 1000 μA μm⁻¹, exceeding the standard of HP applications. Furthermore, the on-state current of OM₂S MOSFETs with 2 nm gate length is about two times higher than that of the LP standard. The EDP value of the sub-5 nm OM₂S MOSFETs can vary from 8.28 × 10⁻³¹ to 2.22 × 10⁻³⁰ J s μm⁻¹ (8.8 × 10⁻³¹ to 3.22 × 10⁻³⁰ J s μm⁻¹) and the value is two orders lower than the standard of HP (LP) applications, resulting in high-speed manipulation and low-energy expending. The subthreshold swing approaches the limit of MOSFETs at room temperature even as the gate length shrinks to 2 nm. This work is expected to provide new opportunities to realize the ultra-short channel electron devices with high performance and low power consumption in the future by utilizing monolayer OGa₂S and OIn₂S semiconductor materials.

Conflicts of interest

There are no conflicts to declare.

Acknowledgements

This work was supported by the National Natural Science Foundation of China (Grant No. 11904085 and 12074103), the Excellent Youth Foundation of Henan Scientific Committee (Grant No. 202300410221), and the Henan Normal University Innovative Science and Technology Team (Grant No. 20200185). The calculations were also supported by the High Performance Computing Center of Henan Normal University.

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Footnote

† Electronic supplementary information (ESI) available. See DOI: https://doi.org/10.1039/d2nr04840j

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