Heqing
Ye‡
ab,
Hyeok-jin
Kwon‡
c,
Ka Yeon
Ryu‡
d,
Kaibin
Wu
b,
Jeongwan
Park
d,
Giri
Babita
d,
Inae
Kim
e,
Chanwoo
Yang
*e,
Hoyoul
Kong
*d and
Se Hyun
Kim
*f
aSchool of Flexible Electronics (SoFE), Henan Institute of Flexible Electronics (HIFE), Henan University, 379 Mingli Road, Zhengzhou 450046, China
bSchool of Chemical Engineering, Konkuk University, Seoul 05029, Korea
cDepartment of Industrial Chemistry, Pukyong National University, Busan 48513, Republic of Korea
dDepartment of Chemistry, Research Institute of Nature Science, Gyeongsang National University, Jinju 52828, Republic of Korea. E-mail: hoyoulkong@gnu.ac.kr
eAdvanced Nano-Surface & Wearable Electronics Research Laboratory, Heat and Surface Technology R&D Department, Korea Institute of Industrial Technology, Incheon 21999, Korea. E-mail: chanu@kitech.re.kr
fSchool of Chemical Engineering, Konkuk University, Seoul 05029, Korea. E-mail: shkim97@konkuk.ac.kr
First published on 27th June 2024
High-k polymeric layers were prepared by combining various functional groups and were applied as gate dielectrics for practical organic field-effect transistors (OFETs). Crosslinking of the polymeric layers through UV-assisted organic azide fluorine-based crosslinkers induced dramatic improvements in the electrical performance of the OFET, such as field-effect mobility and bias-stress stability. Our synthesis and manufacturing method can be a useful technique for ensuring device operation stability and electrical property enhancement. With this analysis, we further applied our polymer-dielectric OFETs to flexible-platform-based electronic components, including unit OFETs and simple logic devices (NOT, NAND, and NOR gates). The outcomes of this research and development suggest a suitable method for the low-cost mass production of large-area flexible and printable devices, using a printing-based approach to replace current processes.
One of the most significant criteria for the practical application of OFETs in electronic components is improving OFET performance while maintaining operational stability. The operational stability of OFETs can be classified in various ways,6,7 most of which are strongly determined by the gate dielectrics. The gate dielectrics in OFETs play a role in lowering the working voltage of the device, limiting the leakage current during operation, and affecting the trap density at the interface between organic semiconductors and insulators.8–11 In particular, leakage current and trap density have a significant impact on the operational stability of the device. As the leakage current characteristic increases, the OFF current level increases, which greatly affects the ratio between ON and OFF currents.12 Additionally, interface traps can create residual charges and shift operational behavior, causing operational instability.7
To date, the most common method for improving the operational stability of OFETs is the treatment of the surface with an inorganic oxide insulating material.13 Inorganic oxide-based dielectrics exhibit excellent insulating properties owing to their high packing densities. When the surface is treated with hydrophobic organic materials, such as various self-assembled monolayer materials, the compatibility with organic semiconductors is enhanced and yields OFETs with good operational stability. However, these high-packing inorganic materials are usually manufactured using expensive vacuum deposition and high-temperature heat treatments.14,15 Additional surface treatment methods often further complicate the manufacturing process. In addition, it is difficult to apply these types of insulating materials to plastic substrates because of their brittleness.16–18
Concerning the above, organic polymeric dielectrics have several advantages over dielectrics made from inorganic materials. Polymeric materials are naturally compatible with organic materials, thereby minimizing the interfacial trap number and improving the electrical performance of OFETs.8 In particular, the desired properties (e.g., mechanical flexibility, hydrophobicity, crosslinking, and solution-processability) can be easily realized through molecular design/synthesis.19–21 Therefore, the common disadvantages of polymers, such as their low leakage properties, mechanical thermal stability, and low dielectric constant (k), can be readily resolved.22,23
Herein, we synthesized a high-k (k > 7) alkyl-based hydrophobic polymeric dielectric material, MBHCa-Ha, for use in the gate dielectrics of OFETs. The prepared material was further modified with an organic azide fluorine-based crosslinker (FPA-3F) to enhance the electrical performance of the OFET, namely the operational stability and interfacial properties. We investigated the effects of crosslinking in polymeric dielectric layers on the morphological and electrical properties and demonstrated a dramatic improvement in device operation. In addition, we manufactured flexible unit OFETs, NOT, NAND, and NOR gates, all of which suggested that the crosslinked layers contributed to robust and stable transistor operation.
After the cleaning and solution preparation processes, Al electrodes were deposited by using a thermal evaporator (2–3 Å s−1, vacuum pressure of 10−6 Torr, and substrate temperature of 25 °C) to a thickness of 30 nm on the cleaned substrates. The polymeric layers were coated by spin coating (2000 rpm for 30 s) or by a printing process using an electrostatic force-assisted dispensing method.24 A thermal annealing process at 120 °C was then conducted for 30 min to eliminate residual solvent. For the crosslinked sample, the crosslinking reaction was conducted under deep UV irradiation (∼254 nm) in an N2-purged glove box.25 Synthesized organic semiconducting layers composed of 2,9-didecyldinaphtho[2,3-b:2′,3′-f]thieno[3,2-b]thiophene (C10-DNTT) were deposited by organic molecular beam deposition as described in previous work.26 The device fabrication process was finished by the deposition of Au source/drain (S/D) electrodes (50 nm) on the sample using a thermal evaporator (2 Å s−1, vacuum pressure of 10−6 Torr, and substrate temperature of 25 °C).
(1) |
With prepared materials, polymeric thin films were deposited using spin-casting and fabricated through the photo-initiated crosslinking process (254 nm UV irradiation).20 Fig. S2† shows that crosslinked patterned FMBHCa-Ha layers were successfully fabricated through line-patterned photomask UV irradiation, indicating the successful crosslinking reaction between MBHCa-Ha and FPA-3F. FPA-3F containing azide moieties functions as a crosslinker with MBHCa-Ha polymers according to the following mechanism described in Fig. S2.† 254 nm UV light irradiation activates the azide moieties (–N3) as a reactive singlet nitrene (–N1) and produces inert nitrogen gas.25 The singlet nitrene group can make connections with alkyl groups (C–H bonds) of the polymer. Through this process, these crosslinked and non-crosslinked (single MBHCa-Ha layer) thin layers were used to assess the polymeric surface properties.
Fig. 1b displays the AFM images of MBHCa-Ha and FMBHCa-Ha. Both had similar topographies and exhibited extremely smooth surfaces (root-mean-square (RMS) roughness < 0.5 nm), regardless of the presence of the crosslinking agent, FPA-3F. The smooth surface provides favorable conditions for the growth of organic semiconducting crystals on the top and non-trapping dielectric surfaces during OFET operation.8 The phase separation phenomenon caused by the aggregation of FPA-3F was not observed in the AFM image of FMBHCa-Ha, owing to uniform mixing between the fluorine-based FPA-3F and MBHCa-Ha; MBHCa-Ha comprising a hydrophilic functional group such as an acrylic-based side chain well mixed with FPA-3F.20 The surface energies of the samples were determined through contact angle measurements using two test liquids (DI water and DII). As shown in Fig. 1c, the pristine MBHCa-Ha thin film and the crosslinked FMBHCa-Ha film exhibited surface energy values of 41.10 and 40.61 mJ m−2, respectively. Similar to the AFM data, the surface energy and contact angle values of the MBHCa-Ha and FMBHCa-Ha were not significantly different.
To verify the insulating properties of the polymeric layers, metal-insulator-metal (MIM) capacitors were prepared with 30 nm of Al and the spin-cast polymeric layers (MBHCa-Ha and FMBHCa-Ha), as shown in the inset of Fig. 1d. The change in the leakage current density value as a function of the applied electric field is shown in Fig. 1d. Both cases displayed highly durable insulation properties until 4 MV cm−1, exhibiting leakage current density values of less than 10−8 A cm−2 at 4 MV cm−1. As the allowable leakage current density limit in the industry is 10−6 A cm2 at 2 MV cm−1, these results imply that the synthesized polymeric layers have relatively good insulation qualities and are suitable for use as gate insulation films for OFETs.
The k-values of the crosslinked and non-crosslinked polymers were extracted from the capacitance measurements in the frequency range of 0.1 to 1000 kHz. The k-values were calculated using the following equation:
(2) |
To test the availability of the synthesized polymeric layers, a bottom-gate top-contact OFET was fabricated. As shown in Fig. 2a, the Al gate electrodes were first coated on the substrates, and the fabrication of the OFET was completed by the sequential deposition of MBHCa-Ha/FMBHCa-Ha, C10-DNTT, and finally Au S/D electrodes. The channel length (L) and width (W) were 100 μm and 1500 μm, respectively. The Ci values of the polymeric layers were measured using an LCR meter which yielded values of 43 and 47 nF cm−2 for MBHCa-Ha and FMBHCa-Ha, respectively. The electrical properties of the fabricated devices were measured in terms of their transmission and output characteristics. The drain current in the saturation zone was monitored in response to a change in the gate voltage (VG) from 20 V to −20 V, while a drain voltage (VD) of −20 V was applied continuously to measure the transfer characteristics. The main electrical parameters of the OFETs, such as the field-effect mobility (μFET), threshold voltage (Vth), and ON-current (Ion)/OFF-current (Ioff) ratio, were determined using the transfer characteristic graph (Fig. 2b) and the following equation:
(3) |
Fig. 2 (a) Schematic image of OFETs with polymeric dielectrics and electrical properties of devices: (b) transfer and (c) output curve (red: MBHCa-Ha, blue: FMBHCa-Ha). |
C i (nF cm−2) | μ FET (cm2 V−1 s−1) | I on/Ioff | V th (V) | SS (mV dec−1) | |
---|---|---|---|---|---|
MBHCa-Ha | 43 | 0.15 ± 0.01 | ∼108 | 4.38 ± 0.31 | 412 |
FMBHCa-Ha | 47 | 1.33 ± 0.05 | ∼108 | −1.34 ± 0.17 | 612 |
The observed electrical properties (transfer and output curves) of the crosslinked devices were clearly superior to those of the non-crosslinked devices. The MBHCa-Ha devices exhibited an Ion of ∼1.5 × 10−5 A, while the FMBHCa-HA devices exhibited an Ion of ∼1 × 10−4 A, even with similar Ci values. This order of magnitude difference between the on-current values caused a large difference in the μFET value (0.15 cm2 V−1 s−1 for MBHCa-Ha and 1.33 cm2 V−1 s−1 for FMBHCa-Ha) and the output curve. The only difference in device configuration was the addition of the crosslinking agent (FPA-3F) and the subsequent crosslinking reaction; the resulting performance improvements were attributed to the degree of crosslinking.
As shown in Fig. 3a, the addition of FPA-3F led to slight vertical phase separation by surface energy minimization.22 The wide-range XPS data shown in Fig. 3b show the contents of the MBHCa-Ha and FMBHCa-Ha layers. As the pristine polymer MBHCa-Ha is only composed of oxygen and carbon (as per Fig. 1a), the observed atomic contents were primarily carbon and oxygen, while additional fluorine was observed in the crosslinked FMBHCa-Ha. Atomic weight distributions of the surface, extracted from the XPS data, showed that the percentages of carbon, oxygen, and fluorine were 72.47, 27.17, and 0.36%, respectively, for MBHCa-Ha, and 73.69, 25.2, and 1.11%, respectively, for FMBHCa-Ha. It can be confirmed that there was a decrease in oxygen-attached functional groups on the polymer surface owing to the addition of the crosslinking agent.
The crosslinking reaction and subsequent change in atomic weight distribution caused a significant change in the morphology of the organic semiconductor, C10-DNTT. Fig. 3c shows a topographic image of the 50 nm C10-DNTT layers deposited on MBHCa-Ha and FMBHCa-Ha. Both cases exhibited mixed crystals composed of smooth pancake-shaped grains and sharp needle-like lamellar grains protruding on the surface. The direction of the lamellar grains indicates the orientation of C10-DNTT. As these individual grains were generated from different nuclei, the orientations of the grains were random.32 However, the grains of C10-DNTT on FMBHCa-Ha were found to be much larger than those of C10-DNTT on MBHCa-HA. Although the surface energy values were similar between the two cases (as shown in Fig. 1c), the addition of the crosslinking agent caused an increase in the hydrophobic functional groups present on the surface, as indicated in the XPS data. Therefore, larger-grain crystals were formed. This result is similar to that in a previous report whereby an organic–inorganic hybrid material was synthesized with a similar surface energy of hydrophobic organic polymeric materials (e.g. cyclo olefin polymers), but with smaller crystals, than were formed in our hydrophobic organic polymer material.24,25,33 The resulting large-grain morphology of C10-DNTT, caused by deposition on our polymer dielectric, improves the charge transfer characteristics. This can be attributed to the presence of fewer charge-trapping sites, such as grain boundaries, between crystal grains.34
In addition to the electrical transport characteristics, the operation stability is also an important part. As shown in the transfer curve in Fig. 2b, regardless of whether a cross-linking agent was applied, both cases showed low hysteresis behavior. Also, electrical operation stability tests were performed using two methods. Fig. 3d shows the sweep-rate-dependence transfer curve data for the MBHCa-Ha- and FMBHCa-Ha-based devices. The transfer curves were measured at different sweep rates of VG: fast sweep conditions were measured with a hold time of 0 s, a sweep delay of 0 s, and 101 data points; slow sweep conditions were measured with a hold time of 0 s, a sweep delay of 1 s, and 101 data points. There was no discernible variation in the degree of response of either device as a function of the gate bias sweep rate, implying that there was no dipole imbalance in the dielectric layers. In addition, the bias-stress stability was identified at ambient temperature and atmospheric pressure with a gate bias-stress (−20 V) at a specific time (0 min to 72 min). As shown in Fig. 3e, the shift in the transfer curve due to the gate bias stress was almost small in both cases (<1 V). The pristine case without the crosslinker induced the low trapping characteristics because of the presence of many non-polar alkyl groups in polymer's molecular structure. Besides, the addition of a fluorinated crosslinker case with surface modification still remained with excellent bias-stress stability properties. This was attributed to deep ionization energy due to the fluorine-based functional groups present on the surface of the crosslinked polymer (fluorine withdraws the electrons very well), which greatly increased the energy barrier between the ionization energy of dielectrics and the highest occupied energy level of C10-DNTT to be overcome for driving the p-type OFETs.35,36
Additionally, the interfacial trap density (Ntrap) values of device through transfer curve data, including bulk and shallow traps, were calculated with the following equation:
(4) |
Based on the above analyses (performance and operation stability), we used the crosslinked polymer layers to manufacture practical flexible printed electronics. FMBHCa-Ha layers were printed on PET films to create a large-area OFET array, and its features were examined to confirm reproducibility (Fig. 4a). Before verifying the OFET properties, the leakage current density of the flexible MIM platform on the PET substrate was observed. Fig. 4b shows the leakage current density according to the bending cycles and the images captured while measuring the leakage current in a bending glass tube (radius 4 mm). Because the crosslinked polymeric layers were flexible, good insulation properties were maintained even under bending (leakage current density < 10−8 A cm−2 at 4 MV cm−1 after 1000 bending cycles).
A flexible OFET array was prepared, and its conventional electrical properties (transfer curve, output curve, and bias-stress stability) were measured, as shown in Fig. 4c. Similar to rigid-platform OFETs, our p-type devices on flexible substrates exhibited stable operation and high uniformity in device performance. In addition, the transfer curves of the flexible OFET displayed robustness under bias-stress conditions, indicating excellent electrical stability. In particular, the OFETs on the flexible platforms exhibited average μFET values of 0.94 cm2 V−1 s−1, with a standard deviation of 0.013 across 64 devices. The ability to fabricate a device with such excellent electrical stability with high reproducibility is promising for the potential large-scale integration of such a unit device.
To confirm this possibility, simple logic devices were prepared on the PET substrates. The manufactured circuit schematics and top-view OM images of the logic gates are shown in Fig. 5a. Diode-connected OFETs as the load transistors and standard p-type OFETs as the driving transistors were coupled in series to create NOT gates. The W/L ratios for the load and drive transistors were 2 (W: 100 μm; L: 200 μm) and 20 (W: 100 μm; L: 2000 μm), respectively. Fig. 5b depicts the operation behavior of our NOT gates, showing voltage transfer characteristics (VTC) and voltage gain curves with supply biases (VDD) of 10, 20, and 30 V. According to the VTC, the output voltage (VOUT) assumed values close to VDD under low input voltage (VIN) conditions and values close to zero under high VIN conditions. Because the gate-source voltage of the driving transistor is small in a high VIN bias state, the load transistor is aggressively switched on, resulting in low current characteristics. Consequently, VOUT was reduced to zero. However, a low VIN bias state results in comparable gate-source voltages for both the drive and load transistors. In our device, the W/L ratio of the driving transistor was much larger than that of the load transistor, and VOUT was pushed up against VDD. Therefore, the “0” and “1” signals of the bias can be referred to as low and high voltage input or output conditions, respectively. The output of the NOT gates is the inverse of the input circumstance; therefore an input voltage signal of “0” results in an output voltage signal of “1”, and vice versa. The VTC curve was used to extract the gain values of these NOT gates (dVOUT/dVIN), which showed maximum values of 9.89, 13.18, and 22.9 for 10, 20, and 30 V, respectively.
Furthermore, one load OFET and two drive OFETs were utilized to create integrated circuit NAND and NOR gates, as shown in Fig. 5a. Two p-type driving OFETs were connected in parallel with each other in the case of the NAND gates. We noticed that the output signal for the produced NAND gates was driven by various logic input signals (see the NAND output signal in Fig. 5c). Both OFETs were turned on when both inputs were in logic-low states, that is, when VA and VB were equal to 0 V, resulting in a straight link between VDD and VOUT. As a result, the output signal was logic-high. Similarly, when one of the inputs was logic-high and the other was logic-low, either of the parallel transistors was operated and VDD and VOUT were connected directly. Therefore, the output signal was logic-high. However, when both inputs were in logic-high states (10 V of input bias), none of the parallel transistors worked, causing the ground (GND) to connect directly to VOUT. As a result, the output signal of the NAND gates was in a logic-low state. Two p-type drive OFETs were connected in series to provide the NOR gates. The series-connected OFETs were turned on when both inputs were in a logic-low state of 0 V input bias at VA and VB, resulting in the establishment of a direct channel between VDD and VOUT (see the NOR output signal in Fig. 5c). In this case, the output signal was in a logic-high state. When any of the inputs was logic-high (greater than 30 V), one or more drive transistors were turned off, causing VDD and VOUT to be disconnected. Consequently, the signal output was logic-low. This operation coincided with that of conventional logic gate drives, indicating that our crosslinked dielectric OFETs were successfully applied to practical integrated circuits.
Footnotes |
† Electronic supplementary information (ESI) available. See DOI: https://doi.org/10.1039/d3na01018j |
‡ H. Ye, H. Kwon and K. Y. Ryu contributed equally to this study. |
This journal is © The Royal Society of Chemistry 2024 |