Achieving neuronal dynamics with spike encoding and spatial-temporal summation in vanadium-based threshold switching memristor for asynchronous signal integration

Abstract

Artificial neuronal devices that emulate the dynamics of biological neurons are pivotal for advancing brain emulation and developing bio-inspired electronic systems. This paper presents the design and demonstration of an artificial neuron circuit based on a Pt/V/AlO_x/Pt threshold switching memristor (TSM) integrated with an external resistor. By applying voltage pulses, we successfully exhibit the leaky integrate-and-fire (LIF) behavior, as well as both spatial and spatiotemporal summation capabilities, achieving the asynchronous signal integration. Notably, the Pt/V/AlO_x/Pt TSM demonstrates ultrafast switching speeds (on/off times ∼165 ns/310 ns) and remarkable stability (endurance >10² cycles with cycle-to-cycle variations <2.5%). These attributes render the circuit highly suitable as a spike generator in neuromorphic computing applications. The Pt/V/AlO_x/Pt TSM-based spike encoder can output current spikes at frequencies ranging from approximately 200 kHz to 800 kHz. The modulation of output spike frequency is achievable by adjusting the external resistor and capacitor within the spike encoder circuit, providing considerable operational flexibility. Additionally, the Pt/V/AlO_x/Pt TSM boasts a lower threshold voltage (V_th ∼ 0.84 V) compared to previously reported VO_x-based TSMs, leading to significantly reduced energy consumption for spike generation (∼2.75 nJ per spike).

---

New concepts

This work presents an energy-efficient threshold switching memristor (TSM) in the stack of Pt/V/AlO_x/Pt. The designed device shows the notable switching speeds (approximately 165 ns for switching on and 310 ns for switching off) and exceptional cycle-to-cycle stability (variations less than 2.5%), providing a reliable component for neuromorphic systems. Based on the proposed Pt/V/AlO_x/Pt TSM, a simple artificial neuron circuit is constructed, and the circuit successfully emulates the neuronal dynamics in the biological neurons. By implementing the neuronal circuit, we achieve the temporal summation and spatial-temporal summation, enabling the neuronal circuit to integrate the asynchronous signal. Furthermore, the circuit effectively converts voltage pulses into current spikes across a wide frequency range, offering substantial flexibility in its operation. The essential features in neuromorphic computing are achieved with our simple neuronal circuit.

1. Introduction

The rapid advancement in neuromorphic computing has generated significant interest in developing artificial neuronal devices that can emulate the functionality of biological neurons.^1–4 Traditional artificial neural networks (ANNs) have achieved remarkable success in various applications; however, their high energy consumption and computational demands pose substantial challenges. Spiking networks (SNNs) offer a more efficient and biologically plausible approach by utilizing the temporal dynamics of spikes, which is similar to the operation of the human brain.^5–7

SNNs consist of three essential components: artificial neurons,^8–10 synapse^11–13 and spike encoders.^14–16 Artificial neurons are fundamental units in integrating and processing spike trains, emulating the complex functionalities of biological neurons.^17–22 They perform essential tasks such as spatial summation and spatiotemporal summation,^23,24 which are crucial for robust signal integration and information processing. On the other hand, spike encoders convert input signals into spike trains using schemes like rate coding,^19,25,26 which translates the intensity of input signals into the frequency of output spikes. This makes rate coding a fundamental technique for information processing in SNNs.

Currently, the hardware implementation of SNNs predominantly relies on CMOS-based architectures.^27–29 While CMOS technology provides high-speed and low-power advantages, designing complex SNN circuits with CMOS presents significant challenges. The intricacy of integrating numerous neurons and synapses, along with the high interconnect density required for effective communication, results in complex and large-scale circuitry. This complexity not only increases the difficulty of design and fabrication but also impacts the scalability and energy efficiency of SNN hardware.

Here, we provide a comprehensive analysis of the Pt/V/AlO_x/Pt TSM device, its implementation in an artificial neuron circuit, and its application as a rate coding spike encoder. We introduce a novel Pt/V/AlO_x/Pt threshold switching memristor (TSM)-based device that exhibits excellent threshold switching characteristics and cycle-to-cycle stability. The following sections include detailed device fabrication and characterization, an examination of its electrical properties and the threshold switching mechanism of the Pt/V/AlO_x/Pt TSM device.

The proposed TSM device is integrated with a simple resistor to construct an artificial neuron circuit, demonstrating its capability to emulate the spatial summation and spatiotemporal summation characteristics of biological neurons. These properties enable our artificial neuron to process spatiotemporal information effectively, which enhances its potential for neuromorphic computing applications by allowing more complex and efficient information processing. Furthermore, we employ the same circuit to function as a spike encoder, demonstrating its capability for rate coding.³⁰ By adjusting the amplitude of the input voltage pulses, the encoder can modulate the frequency of the output current spikes across a wide range (200 kHz to 800 kHz), showing its ability in handling dynamic signal variations. Additionally, compared to other VO_x-based TSMs, the Pt/V/AlO_x/Pt TSM exhibits a lower threshold voltage,^20,31–33 resulting in lower operational voltage and reduced energy consumption. By addressing the critical need for advanced spike encoding techniques, this research contributes to the development of more efficient and adaptable SNNs, paving the way for further advancements in spiking neuromorphic systems.

2. Results and discussion

2.1. Concept of artificial neuron and structure of Pt/V/AlO_x/Pt TSM device

In the left panel of Fig. 1a, the biological neuron integrates spike signals transmitted by the presynaptic neuron. Upon receiving these spikes, the neuron's membrane potential is increased. When the membrane potential reaches the threshold, the neuron fires an action potential, which is subsequently transmitted to the postsynaptic neuron. Conversely, if the membrane potential does not reach the threshold and the neuron ceases to receive spike signals, the membrane potential will gradually decay to its initial resting state. The leaky-integrate-and-fire (LIF) neuron model accurately represents these dynamic properties of biological neurons. This study aims to emulate the LIF function of biological neurons using artificial neurons based on threshold switching memristor (TSM) devices and electronic components (the right panel of Fig. 1a), which is crucial for achieving advanced brain emulation and developing bioinspired electronic systems.

Fig. 1 Comparison of biological and artificial neurons, and schematic and material analysis of the Pt/V/AlO_x/Pt TSM device (a) schematic diagram of an artificial neuron circuit using electronic components to mimic biological neuron behavior. (b) Device structure of the Pt/V/AlO_x/Pt threshold switching memristor (TSM). (c) TEM cross-sectional image of the Pt/V/AlO_x/Pt TSM device. The insets on the right show the crystalline V top electrode and the amorphous AlO_x dielectric layer. (d) HAADF image of the Pt/V/AlO_x/Pt TSM device with corresponding EDS mapping analysis of Pt, V, Al, Ti, and O elements. (e) Schematic illustration of XPS analysis positions on Pt/V/AlO_x/Pt TSM device and the raw data for the V element at each position.

Fig. 1b illustrates the schematic representation of the Pt/V/AlO_x/Pt threshold switching memristor (TSM) device fabricated on a SiO₂ substrate, as utilized in this study. Each layer was deposited via RF sputtering. For all subsequent electrical measurements, voltage was directly applied to the device's protective Pt layer. The thickness of each layer was confirmed through cross-sectional transmission electron microscopy (TEM) imaging, as shown in Fig. 1c. The protective Pt layer is 38.93 nm thick, the top V electrode is 93.71 nm, the AlO_x dielectric layer is 28.10 nm, and the bottom Pt electrode is 95.70 nm. In the high-magnification TEM image, the V layer exhibits a crystalline phase, while the AlO_x layer is amorphous. A high-angle annular dark field scanning transmission electron microscopy (HAADF STEM) image of the Pt/V/AlO_x/Pt TSM device is shown in Fig. 1d. The energy-sispersive X-ray spectroscopy (EDS) elemental mapping results further confirm the elemental distribution within the device. The spatial distribution of Pt, V, Al, Ti, and O elements is clearly illustrated, with distinct boundaries. To verify whether the top electrode V of the Pt/V/AlO_x/Pt memristor device has oxidized after the fabrication process, XPS analysis was conducted, as shown in Fig. 1e. The analysis focuses on the top electrode V. According to the literature, the binding energy of V(0) 2p_3/2 is approximately 512.35 ± 0.3 eV. The positions N1 to N5, corresponding to the approximate locations for XPS analysis, are indicated in the left panel of Fig. 1e, while the right panel displays the corresponding V(0) 2p_3/2 XPS spectra. The results show that the binding energy of V(0) 2p_3/2 at these five positions is consistently around 512.391 eV, aligning with the binding energy of V(0) 3/2 as reported in the literature. There are no significant shifts in the V(0) 2p_3/2 peaks among these positions, suggesting that the top electrode V in the Pt/V/AlO_x/Pt TSM device has retained its metallic state after the fabrication process.

2.2. Pt/V/AlO_x/Pt TSM device-based artificial neuron

The fundamental electrical properties of the Pt/V/AlO_x/Pt TSM device and the operational mechanism of the artificial neuron circuit constructed with this device are illustrated in Fig. 2. Fig. 2a presents the current–voltage (I–V) characteristics of the Pt/V/AlO_x/Pt TSM, obtained after 100 cycles of both positive and negative voltage sweeps following the forming process (Fig. S1, ESI†). Applying positive voltage sweeps (0 to 2 to 0 V), a compliance current (I_cc) of 2 mA was utilized to prevent permanent damage to the device. When the bias voltage exceeded the TSM's threshold voltage (V_th) of approximately 0.82 V, the current abruptly increased to the I_cc level, indicating a transition from a high resistance state (HRS) to a low resistance state (LRS). As the bias voltage decreased below the hold voltage (V_hold) of approximately 0.37 V, a sudden drop in current was observed, demonstrating the typical threshold switching during the positive voltage sweep. Threshold switching was observed when the device was subjected to negative voltage sweeps, confirming that the Pt/V/AlO_x/Pt memristor device exhibits bipolar threshold switching characteristics. The variation of the Pt/V/AlO_x/Pt TSM device was studied due to its potential impact on artificial neural networks. The cycle-to-cycle variations of Pt/V/AlO_x/Pt TSM was analysed, shown in Fig. 2b, and its device-to-device variations were also demonstrated in Fig. S2 and S3 (ESI†). Fig. 2b presents the threshold switching voltages measured from 100 I–V cycles under both positive and negative voltage sweeps. The distributions of positive and negative threshold voltages (V_th) and hold voltages (V_hold) were fitted with Gaussian functions. The mean values for positive V_th, positive V_hold, negative V_th, and negative V_hold were 0.804 V, 0.3636 V, −0.8396 V, and −0.3815 V, respectively, with corresponding σ/μ values of 1.84%, 2.23%, 2.16%, and 2.42%. Given that these variations are all less than 5%, the device demonstrates excellent cycle-to-cycle stability, indicating reliable performance under repeated operations.

Fig. 2 Basic electrical properties of the Pt/V/AlO_x/Pt TSM device and its implementation in an artificial neuron circuit: (a) I–V curves showing 100 cycles of positive and negative voltage sweeps. (b) Distribution of threshold voltages and hold voltages under 100 cycles of voltage sweeps. (c) Switching time for high-to-low and low-to-high resistance states. (d) Artificial neuron circuit using the TSM device, with R_S as the series resistor and C_p as the parasitic capacitor. (e) Voltage pulse waveform applied to the circuit: 3 V amplitude, 2 μs width, 1 μs interval, 20 pulses. (f) Experimental data: red line shows voltage across the TSM device (accumulated capacitor voltage), blue line shows current at the ground terminal.

Fig. 2c investigates the switching time of the Pt/V/AlO_x/Pt TSM device. A voltage pulse with an amplitude of 1 V and a width of 1 μs was applied to the top electrode of the Pt/V/AlO_x/Pt device while grounding the bottom electrode, and the current was measured through the ground terminal. The switching on time was determined as the time difference between the applied voltage reaching the device's V_th (0.82 V) and the current reaching the set compliance current (CC: 11 mA), indicating the transition from HRS to LRS Conversely, the switching off time was measured as the time difference between the applied voltage dropping below V_hold (0.37 V) and the current decreasing to zero, indicating the transition from LRS to HRS. The results show that the switching on time is approximately 165 ns, and the switching off time is approximately 310 ns, demonstrating the device's rapid resistance switching capability, which can be effectively driven by short voltage pulses. To replicate the action potential release characteristic of biological neurons, we constructed a simplified artificial neuron circuit based on the Pt/V/AlO_x/Pt TSM device. Fig. 2d presents a schematic diagram of the Pt/V/AlO_x/Pt TSM-based artificial neuron circuit, comprising a resistor (R_S), a capacitor (C_p), which represent parasitic capacitance of TSM device. The voltage across C_p, corresponding to the TSM voltage, is measured at the red-marked node to demonstrate potential accumulation, while the current at the grounded terminal is measured at the blue-marked node.

The charging and discharging dynamic of C_p play a significant role in the operation of this Pt/V/AlO_x/Pt TSM-based artificial neuron circuit. To elucidate this further, we provide a brief explanation of the principles governing capacitor charging and discharging in the Note of the ESI.† When a voltage pulse train is applied to the Pt/V/AlO_x/Pt TSM-based artificial neuron circuit, as depicted in Fig. 2e, the C_p charges along the yellow path illustrated in Fig. 2d, increasing the voltage across C_p. Simultaneously, the C_p discharges through the TSM device along the blue path shown in Fig. 2d with the device in its high resistance state (HRS). During the intervals between voltage pulses, the absence of an input voltage stimulus allows the discharging effect to dominate, resulting in a decrease in the accumulated voltage across the C_p. As the voltage pulse train continues to be applied to the circuit, the accumulated voltage across C_p steadily increases. When the voltage across C_p reaches the V_th of the TSM device, the device transitions from HRS to LRS. At this point, C_p begins to discharge, leading to a voltage drop across the C_p and sharp current spike at the ground terminal. As the accumulated voltage across the C_p drops to V_hold, the TSM device reverts to HRS, the C_p start charge again. This cyclic process persists as long as the voltage pulses are applied, resulting in continuous fluctuations in the accumulated voltage across C_p and successive current spikes at the grounded terminal, as shown in Fig. 2f. In practical applications, we utilize the main current spikes to emulate the action potential of biological neurons, rather than the multiple peaks in V_out, which are used only to demonstrate potential integration. Additionally, the minor current peaks observed between main spikes are about 100 μA, significantly lower than the 2.5 mA main spikes, and therefore do not present any issues.

In summary, in the Pt/V/AlO_x/Pt TSM-based artificial neuron, the increase in accumulated voltage due to the capacitor's charging mimics the accumulation of membrane potential in biological neurons. When the voltage reaches V_th of the TSM device, the Pt/V/AlO_x/Pt TSM device instantaneously switches to LRS, and accelerating the capacitor's discharge. This transition induces a current spike at the ground terminal, effectively simulating the release of an action potential in biological neurons when the membrane potential reaches its threshold.

2.3. Threshold switching mechanism in Pt/V/AlO_x/Pt TSM device

The vanadium oxides exhibit the insulating-to-metallic transition at the phase transform temperature. Researchers have exploited this property to develop memristors, utilizing Joule heat to induce resistance switching in these materials. Consequently, we infer that VO_x formation occurs in the Pt/V/AlO_x/Pt TSM device during electrical operation, and this VO_x is responsible for the threshold switching characteristics.

We investigate the threshold switching (TS) mechanism of the Pt/V/AlO_x/Pt TSM device, illustrated in Fig. 3. The TS mechanism of the device is elucidated as follows: (i) during the positive voltage sweep, oxygen ions in AlO_x migrate towards the top electrode due to the electric field, leading to the accumulation of oxygen vacancies at the bottom electrode. (ii) As the sweep voltage increases, the accumulation of oxygen vacancies is continued. Eventually, conductive filament bridges the top and bottom electrodes, resulting in a sharp increase in current. (iii) Once the conductive filament is formed, further increases in the applied voltage cause substantial current to flow through this path, generating significant Joule heat. This heating effect induces a reaction between vanadium at the V/AlO_x interface and the migrating oxygen ions, resulting in the formation of VO_x with insulating-to-metallic transition properties. This is reflected in the left panel's current–voltage curve as an additional rise in current. (iv) As the sweep voltage decreases, the current through the device diminishes, and the Joule heat dissipates, causing VO_x to revert from a metallic state to an insulating state. Correspondingly, a sharp decrease in current is observed. However, because the conductive filament of oxygen vacancies remains intact, the device's resistance does not fully return to its initial high resistance state, and the current does not immediately drop to its initial low value.

Fig. 3 Schematic representation of the threshold switching mechanism in the Pt/V/AlO_x/Pt TSM device. The left panel shows the experimentally measured current–voltage (I–V) characteristics of the device. The right panel provides a schematic illustration of the mechanism, with labels (a)–(f) corresponding to the phenomena occurring within the device under applied voltage.

Additionally, we further investigated the influence of varying the thickness of the V top electrode and the AlO_x layer on its threshold switching. Since the TS phenomenon is predominantly induced by VO_x generated at the V/AlO_x interface, alterations in AlO_x thickness exert minimal impact on TS (Fig. S4, ESI†). However, variations in V electrode thickness significantly influence the device's V_th (Fig. S5, ESI†), with thinner V layers resulting in higher V_th due to enhanced thermal dissipation. Conversely, thicker V layers, with superior thermal retention, lower the voltage required to induce the insulating-to-metallic transition in VO_x, resulting in a reduced V_th.

Based on the preceding analysis, the resistance state switching in the Pt/V/AlO_x/Pt TSM device is primarily governed by the metal–insulator transition properties of VO_x at the V/AlO_x interface, along with the controlled formation and rupture of conductive filaments of oxygen vacancies beneath VO_x. To confirm the proposed resistive switching mechanism in our Pt/V/AlO_x/Pt, we analyse the V/AlO_x interface of operated device through the high-resolution TEM as provided in Fig. S6 (ESI†). The HR-TEM image reveals that the V metal near the V/AlO_x interface transitions from a polycrystalline to an amorphous structure. This structural change suggests that oxidation of the V metal occurs during electrical operation. This mechanism also imparts the Pt/V/AlO_x/Pt TSM device with non-volatile resistive switching. (details provided in Fig. S7, ESI†).

2.4. Temporal signal processing and spatial-temporal summation capability in Pt/V/AlO_x/Pt TSM-based artificial neurons

Fig. 4 demonstrates that the Pt/V/AlO_x/Pt TSM-based artificial neuron exhibits the temporal summation, spatial summation, and spatial-temporal summation characteristics observed in biological neurons. We have constructed artificial neuron circuits by wiring the series resistor and TSM on a breadboard setup, shown in Fig. S8 (ESI†). Fig. 4a illustrates the characteristics of a biological neuron in response to stimuli delivered at different time points. Upon receiving stimulus signals, the neuron's membrane potential increases. During the intervals between stimuli, the accumulated membrane potential decays. When the membrane potential reaches the threshold, the neuron fires an action potential, which is then transmitted to adjacent neurons. This capability to integrate successive stimuli, known as temporal summation, is influenced by the temporal intervals between stimuli, thereby affecting the timing of action potential firing. This property endows biological neurons with the ability to process temporally correlated stimuli, enabling complex temporal information processing.

Fig. 4 Temporal signal processing and spatial-temporal summation capabilities of the Pt/V/AlO_x/Pt-based artificial neuron. (a) Temporal summation in a biological neuron. (b) Experimental setup for temporal summation measurement, demonstrating the signal processing capability of the Pt/V/AlO_x/Pt TSM-based artificial neuron with 20 input pulses (3 V amplitude, 3 μs pulse width) and different pulse intervals. (c) Pulse interval: 1 μs. (d) Pulse interval: 3 μs. (e) Pulse interval: 5 μs. (f) Spatial-temporal summation in a biological neuron. (g) Illustration of the experimental setup for spatial-temporal summation measurement, showing the spatial-temporal summation capability of the circuit with two inputs, each receiving 10 pulses (4 V amplitude, 0.8 μs pulse period) with time difference (Δt). (h) Time difference: −4 μs. (i) Time difference: 0 μs. (j) Time difference: +4.8 μs. (k) Time difference: +8.0 μs.

We use the circuit in Fig. 4b to emulate this function. In this setup, the load resistors (R_S) serve as synapses, while C_p in the circuit represents the parasitic capacitance of the TSM device. Three sets of voltage pulse trains, each consisting of 20 pulses were applied to the artificial neuron with pulse intervals of 1 μs, 3 μs, and 5 μs, respectively. The corresponding output responses of the neuron for these pulse intervals are illustrated in Fig. 4c–e. As shown in Fig. 4c, where the pulse interval was 1 μs, nine output current spikes were observed within approximately 60 μs. In contrast, Fig. 4d illustrates that with a pulse interval of 3 μs, the same nine output current spikes were observed, but the required time extended to approximately 100 μs. Finally, in Fig. 4e, where the pulse interval was set to 5 μs, no spikes were observed (additional data with varying pulse intervals can be found in Fig. S9, ESI†).

These observations indicate that the neuron can exhibit different spike output frequencies based on the varying pulse intervals of the input pulse train. When the pulse interval is too long, no spikes are fired. This confirms the artificial neuron's ability to process temporal signals, reflecting the temporal relationship of the input voltage pulses and releasing the corresponding spike trains. (The relationship between the output spike frequency of this artificial neuron and the pulse interval of the input voltage pulses is shown in Fig. S10, ESI†).

The concept of spatial-temporal summation in biological neurons, which refers to their capacity to integrate asynchronous stimuli from different synapses, is depicted in Fig. 4f. To replicate this feature, we employ the circuit illustrated in Fig. 4g. In this setup, the load resistors (R_S1 and R_S2) function as two spatially distributed synapses. Asynchronous voltage pulse trains, each consisting of 10 pulses with a pulse amplitude of 4 V, a pulse width of 0.3 μs, and a pulse interval of 0.3 μs, were applied to the two input terminals of the circuit. Δt is defined as the time difference between the arrival of the two input pulses. A positive Δt is assigned when the voltage pulse train reaches R_S1 before R_S2, while a negative Δt is assigned when R_S1 receives signals after R_S2. Fig. 4h–k presents the output results of the artificial neuron circuit corresponding to Δt of −4 μs, 0 μs, +4.8 μs, and +8 μs, respectively. We set the asymmetric time interval (Δt = −4 μs vs. Δt = +4.8 μs) to demonstrate that integration can occur with input from only R_S2 and how temporal affects spatiotemporal summation processing.

As illustrated in Fig. 4h–k, it is evident that during the periods where the two voltage pulses overlap, the output spike frequency increases, with approximately one spike fired for every two input voltage pulses. Conversely, in the non-overlapping regions, the output spike frequency decreases, resulting in approximately one spike for every four input voltage pulses. The varying degrees of overlap between the input voltage pulses depicted in Fig. 4h–k, resulted in differences in the charging rates of the capacitor within the circuit, ultimately leading to distinct output spike trains.

The charging and discharging characteristics of the capacitor (C_p) can be analogized to the accumulation and leakage of membrane potential in neurons. When the interval of the pulse train is extended, the capacitor experiences a prolonged discharge period, resulting in greater dissipation of accumulated voltage. Consequently, the Pt/V/AlO_x/Pt TSM-based artificial neuron requires more pulses to accumulate sufficient voltage to reach the V_th of the Pt/V/AlO_x/Pt TSM device and trigger a current spike. Conversely, when the pulse interval is shortened, the capacitor's discharge duration is reduced, leading to less voltage loss. As a result, the artificial neuron circuit requires fewer pulses to reach the V_th of the TSM device, enabling the emission of current spikes. These findings confirm that the Pt/V/AlO_x/Pt TSM-based artificial neuron exhibits spatiotemporal summation capabilities, effectively integrating asynchronous input voltage pulses from the two terminals and thereby firing corresponding spike trains. Furthermore, the spatial summation capability of the Pt/V/AlO_x/Pt TSM-based artificial neuron is illustrated in Fig. S11 (ESI†). Notably, the key factor in signal integration is the charging and discharging rates of the device's parasitic capacitance, which are independent of the switching ratio. Therefore, switching ratio does not impact the performance of signal integration.

2.5. Pt/V/AlO_x/Pt TSM-based spike encoder

Rate coding is the predominant encoding method in spiking neural networks (SNNs). In image recognition tasks, the image is segmented into individual pixels, each of which is converted into a spike train. The spike frequency correlates with the pixel intensity: darker pixels generate higher frequency spike trains, while lighter pixels produce lower frequency spike trains. The image is thus represented by spike trains of distinct frequencies corresponding to each pixel. These spike trains are fed into the SNN, which processes the patterns to perform tasks such as image recognition by interpreting the spike patterns and making predictions based on learned features.

In Fig. 5 demonstrates the capability of the Pt/V/AlO_x/Pt TSM-based circuit as a spike encoder for rate coding, which can be analogized to a Pearson–Anson oscillator.³⁴ The relationship between oscillation frequency and input voltage described by eqn (1).

Here, R_S represents the series resistor in the spike encoder, C_p denotes the parasitic capacitance of the TSM, V_in is the applied voltage, and V_th and V_hold are the threshold and holding voltages of the TSM, respectively. In eqn (1), the switching ratio has no effect on the spiking frequency. Therefore, switching ratio does not impact the performance of the spike encoder.

Fig. 5 Pt/V/AlO_x/Pt TSM-based spike encoder. (a) Schematic illustration of the rate coding scheme in spiking neural networks (SNN). (b) Circuit diagram of the Pt/V/AlO_x/Pt TSM-based spike encoder. (c) Voltage oscillation characteristic of the Pt/V/AlO_x/Pt TSM under applied voltage pulses. (d) Output current spike trains generated at various frequencies by the spike encoder. (e) Relationship of input voltage amplitude and output current spike frequency. (f) Real-time response and generation of the corresponding current spike train in response to stepwise voltage stimulation.

The measurement setup, illustrated in Fig. 5b, includes R_S1, a 9.1 kΩ series-connected resistor with the TSM device, and C_p, the parasitic capacitance of the TSM device. The red dot node denotes the oscilloscope connection point for monitoring voltage oscillations across the Pt/V/AlO_x/Pt TSM device, while the blue dot node indicates the grounding point for observing current spikes. By applying voltage pulses of varying amplitudes to the circuit, we observe the voltage oscillations across the TSM device and current spikes are released. Fig. 5c and d present the voltage oscillations across the TSM device and the output current spikes in relation to the amplitude of the input voltage pulse. The voltage oscillations across the Pt/V/AlO_x/Pt TSM device become more significant with increasing input voltage pulse amplitudes, resulting in a corresponding increase in the frequency of the output current spikes. Fig. 5e delineates the relationship between the input voltage pulse amplitude and the output current spike frequency. With an input voltage of 3 V, the encoder outputs current spikes at a frequency of 231 kHz. When the input voltage is increased to 7 V, the output current spike frequency reaches 725 kHz. The positive correlation between the voltage oscillation frequency and the output spike frequency with the amplitude of input voltage pulse is due to variations in the charging rate of the parasitic capacitance of the Pt/V/AlO_x/Pt TSM device. Higher input voltages accelerate charging, enabling the voltage to reach the TSM device's V_th more quickly, thus triggering faster current spikes. Conversely, lower input voltages slow voltage accumulation, reducing both the voltage oscillation frequency and the current spiking rate, which demonstrates that the encoder possesses a substantial tuning range for the output current spike frequency is controlled by the input voltage pulse amplitude. The highly linear correlation between the input pulse amplitude and the output frequency indicates that the Pt/V/AlO_x/Pt TSM-based encoder can be easily adjusted, offering significant flexibility. In Fig. 5f, the Pt/V/AlO_x/Pt TSM-based spike encoder is evaluated using an input voltage pulse with stepwise varying amplitudes to observe its real-time response and output the corresponding current spike train. The input voltage is incremented from 3 V to 4 V, then to 5 V, and finally to 6 V. The results demonstrate that the encoder effectively outputs current spikes at frequencies corresponding to the varying input voltage amplitudes. This confirms the spike encoder's ability to respond to continuous voltage changes and produce corresponding current spike trains, highlighting its capability to handle dynamic signal variations. Furthermore, as illustrated in Fig. S12 and S13 (ESI†), the output current spike frequency of this spike encoder circuit can be finely tuned by adjusting the external series resistor and parallel capacitor values, enabling precise modulation of the target spike frequency range and enhancing the flexibility of circuit configuration for various applications.

On the previous study, we utilized the Pt/V/AlO_x/Pt TSM as the crucial component of the artificial neuron circuit. Its low V_th and fast switching speed enable the device to operate at low voltages, allowing the constructed artificial neuron circuit and spike encoder to be driven by ultra-short voltage pulses (∼μs range). The energy consumption required to generate a single spike is notably lower compared to values reported in other studies (calculated as 2.75 nJ per spike, as detailed in Fig. S14, ESI†). Furthermore, the Pt/V/AlO_x/Pt TSM-based artificial neuron exhibits key neuronal functions in biological neurons, such as spatial summation and spatiotemporal summation, demonstrating its ability to integrate both temporal and spatial signals. These features, combined with its low energy consumption and fast switching speed, position the Pt/V/AlO_x/Pt TSM-based artificial neuron as a promising and competitive candidate for future neuromorphic hardware architectures. For a comprehensive comparison with existing studies, please refer to the comparison table provided in the ESI,† (Table S1).

3. Conclusions

In conclusion, the Pt/V/AlO_x/Pt TSM-based artificial neuron and spike encoder demonstrate significant advancements for neuromorphic computing applications. The artificial neuron circuit, leveraging the Pt/V/AlO_x/Pt TSM, successfully emulates the leaky integrate-and-fire and spatial and spatiotemporal summation capabilities akin to biological neurons. The device's rapid switching speed (∼165 ns for switching on and ∼310 ns for switching off) and high cycle-to-cycle stability (variations < 2.5% over 102 cycles) make it a robust component for neuromorphic systems. The Pt/V/AlO_x/Pt TSM-based spike encoder effectively converts voltage pulses into current spikes, with output frequencies ranging from 200 kHz to 800 kHz. This functionality, combined with the low threshold voltage (V_th ∼ 0.84 V) and reduced energy consumption (∼3.42 nJ per spike), highlights the encoder's efficiency and adaptability. The ability to modulate output spike frequency by adjusting external resistors and capacitors enhances the circuit's operational flexibility. These findings underscore the potential of Pt/V/AlO_x/Pt TSM devices in developing more energy-efficient and scalable neuromorphic computing hardware.

4. Experimental methods

4.1. Device fabrication

The Pt/V/AlO_x/Pt TSM device was fabricated at room temperature. First, the highly boron-doped p⁺-Si substrate underwent RCA cleaning to remove surface contaminants. A SiO₂ layer was then thermally grown on the cleaned p⁺-Si substrate using a thermal oxidation process. Subsequently, a Ti adhesion layer and Pt bottom electrode were deposited on the substrate using RF magnetron sputtering. Following this, an AlO_x dielectric layer was deposited on the Pt bottom electrode using an Al₂O₃ ceramic target. The total gas flow was set to 60 sccm with an Ar : O₂ ratio of 59 : 1, and during sputtering, the working pressure was maintained at 10 mtorr for 40 minutes. Next, a V top electrode was deposited by DC sputtering. Finally, a Pt protective layer was deposited using RF magnetron sputtering to prevent further oxidation of the V top electrode. The top electrode size of the device was 200 × 200 μm².

4.2. Characterization

The TEM images and EDS analysis were obtained by JEM 2100F field emission transmission electron microscope. The electrical characterization was performed in air at room temperature using a Keysight B1500A semiconductor device parameter analyser. The pulsed current–voltage measurement was recorded by a waveform generator/fast measurement unit (WGFMU). The voltage measurements of the Pt/V/AlO_x/Pt TSM device were conducted using an Agilent DSO6102A oscilloscope.

Author contributions

Pei-Lin Lin: investigation, conceptualization, data curation, formal analysis, methodology and writing the original draft; Zih-Siao Liao: methodology, formal analysis and editing; Shuai-Ming Chen: methodology, formal analysis and editing; Jen-Sue Chen: funding acquisition, supervision and editing. All authors reviewed the manuscript.

Data availability

The data supporting this article have been included as part of the ESI.†

Conflicts of interest

There are no conflicts to declare.

Acknowledgements

This work is supported by National Science and Technology Council, Taiwan under Projects NSTC 113-2223-E-006-004, NSTC 113-2124-M-006-008-MY3 and NSTC 113-2926-I-006-501-G.

References

1. K. He, C. Wang, Y. He, J. Su and X. Chen, Chem. Rev., 2023, 123, 13796–13865.
2. S. Choi, J. Yang and G. Wang, Adv. Mater., 2020, 32, 2004659.
3. L. Wang, P. Zhang, Z. Gao, J. Liu and D. Wen, ACS Sustainable Chem. Eng., 2024, 12, 10387–10398.
4. L. Tang, Y. Huang, C. Wang, Z. Zhao, Y. Yang, J. Bian, H. Wu, Z. Zhang and D. W. Zhang, J. Mater. Chem. C, 2022, 10, 14695–14702.
5. L. Ye, Z. Gao, J. Fu, W. Ren, C. Yang, J. Wen, X. Wan, Q. Ren, S. Gu and X. Liu, Front. Phys., 2022, 10, 839243.
6. L. Deng, Y. Wu, X. Hu, L. Liang, Y. Ding, G. Li, G. Zhao, P. Li and Y. Xie, Neural Networks, 2020, 121, 294–307.
7. K. Sun, J. Chen and X. Yan, Adv. Funct. Mater., 2021, 31, 2006773.
8. J. Wang, C. Teng, Z. Zhang, W. Chen, J. Tan, Y. Pan, R. Zhang, H. Zhou, B. Ding and H.-M. Cheng, ACS Nano, 2021, 15, 15123–15131.
9. H. Liu, T. Wu, X. Yan, J. Wu, N. Wang, Z. Du, H. Yang, B. Chen, Z. Zhang and F. Liu, Nano Lett., 2021, 21, 3465–3472.
10. J.-K. Han, S.-C. Park, J.-M. Yu, J.-H. Ahn and Y.-K. Choi, Nano Lett., 2022, 22, 5244–5251.
11. J. Zhou, H. Li, M. Tian, A. Chen, L. Chen, D. Pu, J. Hu, J. Cao, L. Li and X. Xu, ACS Appl. Mater. Interfaces, 2022, 14, 35917–35926.
12. E. Park, S. Jang, G. Noh, Y. Jo, D. K. Lee, I. S. Kim, H.-C. Song, S. Kim and J. Y. Kwak, Nano Lett., 2023, 23, 9626–9633.
13. S. Ke, Y. Pan, Y. Jin, J. Meng, Y. Xiao, S. Chen, Z. Zhang, R. Li, F. Tong and B. Jiang, ACS Appl. Mater. Interfaces, 2024, 16, 13989–13996.
14. S. Yang, D. Li, J. Feng, B. Gong, Q. Song, Y. Wang, Z. Yang, Y. Chen, Q. Chen and W. Huang, Adv. Electron. Mater., 2024, 2400075.
15. S. Subbulakshmi Radhakrishnan, A. Sebastian, A. Oberoi, S. Das and S. Das, Nat. Commun., 2021, 12, 2143.
16. F. Li, D. Li, C. Wang, G. Liu, R. Wang, H. Ren, Y. Tang, Y. Wang, Y. Chen and K. Liang, Nat. Commun., 2024, 15, 3689.
17. J. Wen, L. Zhang, Y.-Z. Wang and X. Guo, ACS Appl. Mater. Interfaces, 2023, 16, 998–1004.
18. H. Liu, X. Zhu, Z. Guo, R. He, X. Li, Q. Sun, X. Ye, C. Sun, Y. Tian and R.-W. Li, ACS Appl. Electron. Mater., 2023, 5, 3454–3461.
19. R. Yuan, Q. Duan, P. J. Tiw, G. Li, Z. Xiao, Z. Jing, K. Yang, C. Liu, C. Ge and R. Huang, Nat. Commun., 2022, 13, 3973.
20. R. Yuan, P. J. Tiw, L. Cai, Z. Yang, C. Liu, T. Zhang, C. Ge, R. Huang and Y. Yang, Nat. Commun., 2023, 14, 3695.
21. C. Chen, Y. He, H. Mao, L. Zhu, X. Wang, Y. Zhu, Y. Zhu, Y. Shi, C. Wan and Q. Wan, Adv. Mater., 2022, 34, 2201895.
22. X. Wang, C. Chen, L. Zhu, K. Shi, B. Peng, Y. Zhu, H. Mao, H. Long, S. Ke, C. Fu, Y. Zhu, C. Wan and Q. Wan, Nat. Commun., 2023, 14, 3444.
23. S. Zhong, Y. Zhang, H. Zheng, F. Yu and R. Zhao, Adv. Intell. Syst., 2022, 4, 2200076.
24. Q. Duan, Z. Jing, X. Zou, Y. Wang, K. Yang, T. Zhang, S. Wu, R. Huang and Y. Yang, Nat. Commun., 2020, 11, 3399.
25. S. Subbulakshmi Radhakrishnan, S. Chakrabarti, D. Sen, M. Das, T. F. Schranghamer, A. Sebastian and S. Das, Adv. Mater., 2022, 34, 2202535.
26. X. Zhang, Y. Zhuo, Q. Luo, Z. Wu, R. Midya, Z. Wang, W. Song, R. Wang, N. K. Upadhyay and Y. Fang, Nat. Commun., 2020, 11, 51.
27. S. K. Vohra, S. A. Thomas, M. Sakare and D. M. Das, arXiv, 2022, preprint, arXiv:2204.04430 DOI:10.48550/arXiv.2204.04430.
28. S. K. Vohra, S. A. Thomas, M. Sakare and D. M. Das, Integration, 2024, 95, 102122.
29. B. Joo, J.-W. Han and B.-S. Kong, IEEE Trans. Circuits Syst. I, 2022, 69, 3632–3642.
30. W. Guo, M. E. Fouda, A. M. Eltawil and K. N. Salama, Front. Neurosci., 2021, 15, 638474.
31. Y. Fu, Y. Zhou, X. Huang, B. Dong, F. Zhuge, Y. Li, Y. He, Y. Chai and X. Miao, Adv. Funct. Mater., 2022, 32, 2111996.
32. C. Liu, P. J. Tiw, T. Zhang, Y. Wang, L. Cai, R. Yuan, Z. Pan, W. Yue, Y. Tao and Y. Yang, Nat. Commun., 2024, 15, 1523.
33. K. Yang, Y. Wang, P. J. Tiw, C. Wang, X. Zou, R. Yuan, C. Liu, G. Li, C. Ge and S. Wu, Nat. Commun., 2024, 15, 1693.
34. L. Gao, P.-Y. Chen and S. Yu, Appl. Phys. Lett., 2017, 111, 103503.

---

Footnote

† Electronic supplementary information (ESI) available. See DOI: https://doi.org/10.1039/d4nh00484a

---