Quantum transport simulation of α-GeTe ferroelectric semiconductor transistors

Abstract

Ferroelectric semiconductor transistor is a newly proposed device that uses ferroelectric semiconductors as channel materials for integrated memory and computation. Currently, the main challenge in advancing ferroelectric semiconductor transistors (FeS-FETs) is finding ferroelectric channel materials that balance high performance with industrial production feasibility. In this work, we predict the performance of α-GeTe, a quasi-two-dimensional ferroelectric semiconductor with excellent compatibility with Si-based substrates, as a FeS-FET by ab initio quantum transport simulation. When taking negative capacitance technology and underlap structure into account, we find that α-GeTe ferroelectric semiconductor transistors can meet the international technology roadmap for semiconductors for high-performance standards for industrial-grade chip logic operations with a 5-nm channel length, and achieve a ferroelectric switch ratio of 228 at zero gate voltage. The memory window (0.9 V) of the 5-nm gate-length monolayer α-GeTe FeS-FETs is three times larger than that (0.3 V) of the α-In2_Se₃ ferroelectric semiconductor transistor. Our work suggests that α-GeTe is a strong candidate for the future industrial fabrication of FeS-FETs.